| 2018 | ISCA | ACCORD: Enabling Associativity for Gigascale DRAM Caches by Coordinating Way-Install and Way-Prediction. | Vinson Young, Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi |
| 2016 | MICRO | CANDY: Enabling coherent DRAM caches for multi-node systems. | Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi |
| 2015 | DSN | Reducing Refresh Power in Mobile Devices with Morphable ECC. | Chia-Chen Chou, Prashant J. Nair, Moinuddin K. Qureshi |
| 2015 | HPCA | Reducing read latency of phase change memory via early read and Turbo Read. | Prashant J. Nair, Chia-Chen Chou, Bipin Rajendran, Moinuddin K. Qureshi |
| 2015 | ISCA | BEAR: techniques for mitigating bandwidth bloat in gigascale DRAM caches. | Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi |
| 2014 | MICRO | CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache. | Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi |
| 2013 | HPCA | A case for Refresh Pausing in DRAM memory systems. | Prashant J. Nair, Chia-Chen Chou, Moinuddin K. Qureshi |
| 2010 | ICASSP | An initial attempt to improve spoken term detection by learning optimal weights for different indexing features. | Yu-Hui Chen, Chia-Chen Chou, Hung-yi Lee, Lin-Shan Lee |