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Chien-In Henry Chen

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

12

Venues

4

Active years

1989–2009

Best venue rank

A*

Where they publish

Papers

12 indexed papers, newest first.

YearVenueTitleAuthors
2009ISCASDual Thresholding for Digital Wideband Receivers with Variable Truncation Scheme.Yu-Heng George Lee, Chien-In Henry Chen
2008ISCASReal-time FPGA-based implementation of digital instantaneous frequency measurement receiver.Yu-Heng George Lee, James Helton, Chien-In Henry Chen
2005ISCASA low-power 4-b 2.5 Gsample/s pipelined flash analog-to-digital converter using differential comparator and DCVSPG encoder.Shailesh Radhakrishnan, Mingzhen Wang, Chien-In Henry Chen
2003ISCASConfigurable two-dimensional linear feedback shifter registers for deterministic and random patterns [logic BIST].Chien-In Henry Chen, Kiran George
1999ISCASHigh-level design synthesis with redundancy removal for high speed testable adders.Meghanad D. Wagh, Chien-In Henry Chen
1993ICCADLogic partitioning to pseudo-exhaustive test for BIST design.Chien-In Henry Chen, Joel T. Yuen
1992ICCDConcurrent Test Scheduling in Built-In Self-Test Environment.Chien-In Henry Chen, Joel T. Yuen
1992ICCDAutonomous-Tol for Hardware Partitioning in a Built-in Self-Test Environment.Chien-In Henry Chen, Joel T. Yuen, Ji-Der Lee
1991DACGraph Partitioning for Concurrent Test Scheduling in VLSI Circuit.Chien-In Henry Chen
1991ICCADBISTSYN - A Built-In Self-Test Synthesizer.Chien-In Henry Chen
1991ICCDAllocation of Multiport Memory with Ports of Different Type in Register Transfer Level Synthesis.Chien-In Henry Chen
1989ICCDAn efficient approach to pseudo-exhaustive test generation for BIST design.Chien-In Henry Chen, Gerald E. Sobelman