Chin-Fu Chen
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
3
Active years
1984–1988
Best venue rank
A*
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1988 | DAC | An Accurate and Efficient Gate Level Delay Calculator for MOS Circuits. | Foong-Charn Chang, Chin-Fu Chen, Prasad Subramaniam |
| 1988 | DAC | Model Development and Verification for High Level Analog Blocks. | Chandramouli Visweswariah, Rakesh Chadha, Chin-Fu Chen |
| 1988 | ICCAD | M | Rakesh Chadha, Chin-Fu Chen |
| 1988 | ICCD | Extension of a transistor level digital timing simulator to include first order analog behavior. | Rakesh Chadha, Chin-Fu Chen |
| 1984 | DAC | The second generation motis mixed-mode simulator. | Chin-Fu Chen, Chi-Yuan Lo, Hao N. Nham, Prasad Subramaniam |