Chun-hong Chen
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
1998–1999
Best venue rank
B
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1999 | ASPDAC | Timing Optimization of Logic Network Using Gate Duplication. | Chun-hong Chen, Chi-Ying Tsui |
| 1998 | ISLPED | Towards the capability of providing power-area-delay trade-off at the register transfer level. | Chun-hong Chen, Chi-Ying Tsui |