Chun-Yeh Liu
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
1987–1995
Best venue rank
A*
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1995 | VTS | An optimized testable architecture for finite state machines. | Ting-Yu Kuo, Chun-Yeh Liu, Kewal K. Saluja |
| 1987 | DAC | BIST-PLA: A Built-in Self-Test Design of Large Programmable Logic Arrays. | Chun-Yeh Liu, Kewal K. Saluja, Shambhu J. Upadhyaya |