Chung-Hsiang Lin
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
4
Active years
2006–2022
Best venue rank
A*
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2022 | ASPDAC | PUMP: Profiling-free Unified Memory Prefetcher for Large DNN Model Support. | Chung-Hsiang Lin, Shao-Fu Lin, Yi-Jung Chen, En-Yu Jenp, Chia-Lin Yang |
| 2012 | ICCD | SECRET: Selective error correction for refresh energy reduction in DRAMs. | Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang |
| 2010 | MICRO | Memory Latency Reduction via Thread Throttling. | Hsiang-Yun Cheng, Chung-Hsiang Lin, Jian Li, Chia-Lin Yang |
| 2009 | ISLPED | PPT: joint performance/power/thermal management of DRAM memory for multi-core systems. | Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King |
| 2006 | ISLPED | Hierarchical value cache encoding for off-chip data bus. | Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King |