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Chunyan Pei

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

7

Venues

4

Active years

2024–2026

Best venue rank

A*

Where they publish

Papers

7 indexed papers, newest first.

YearVenueTitleAuthors
2026ASPDACTiming-Aware Optimization of Die-Level Routing and TDM Assignment for Multi-FPGA Systems.Yijun Chen, Haoyuan Li, Chunyan Pei, Jianwang Zhai, Kang Zhao, Wenjian Yu
2026ASPDACAutomated Parameter Tuning for Multi-FPGA Partitioning: A Preference-Guided Approach.Yutao Dai, Shengbo Tong, Chunyan Pei, Zhuohua Liu, Wei Xing, Yi Liu, Rui Wang, Wenjian Yu
2026DATEHGNN-Part: A High-Quality Hypergraph Partitioner Based on Hypergraph Generative Model.Shengbo Tong, Rufan Zhou, Chunyan Pei, Wenjian Yu
2025ASPDACEfficient Hypergraph Modeling of VLSI Circuits for the MFS-Based Emulation and Simulation Acceleration.Jiahao Xu, Chunyan Pei, Shengbo Tong, Wenjian Yu
2025ASPDACDeep Learning Inspired Capacitance Extraction Techniques.Wenjian Yu, Shan Shen, Dingcheng Yang, Haoyuan Li, Jiechen Huang, Chunyan Pei
2025DACBlasPart: A Deterministic Parallel Partitioner for Balanced Large-Scale Hypergraph Partitioning.Shengbo Tong, Chunyan Pei, Wenjian Yu
2024ICCADEasyPart: An Effective and Comprehensive Hypergraph Partitioner for FPGA-based Emulation.Shengbo Tong, Haoyuan Li, Jiahao Xu, Chunyan Pei, Wenjian Yu, Shengjun Liu, Jian Shen