Clarence S. P. Lee
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2006–2006
Best venue rank
B
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2006 | FPL | Power Implications of Implementing Logic Using FPGA Embedded Memory Arrays. | Scott Y. L. Chin, Clarence S. P. Lee, Steven J. E. Wilton |