Costin Anghel
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
3
Active years
2012–2017
Best venue rank
C
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2017 | DATE | Tunnel FET based refresh-free-DRAM. | Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel |
| 2017 | ETS | Refresh frequency reduction of data stored in SSDs based on A-timer and timestamps. | Marcelino Seif, Emna Farjallah, Franck Badets, Emna Chabchoub, Christophe Layer, Jean-Marc Armani, Francis Joffre, Costin Anghel, Luigi Dilillo, Valentin Gherman |
| 2016 | DATE | 3T-TFET bitcell based TFET-CMOS hybrid SRAM design for Ultra-Low Power applications. | Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel |
| 2016 | ISCAS | Ultra-compact SRAM design using TFETs for low power low voltage applications. | Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel |
| 2015 | ISCAS | Ultra-low leakage sub-32nm TFET/CMOS hybrid 32kb pseudo DualPort scratchpad with GHz speed for embedded applications. | Navneet Gupta, Adam Makosiej, Oliver Thomas, Amara Amara, Andrei Vladimirescu, Costin Anghel |
| 2012 | ISCAS | A 32nm tunnel FET SRAM for ultra low leakage. | Adam Makosiej, Rutwick Kumar Kashyap, Andrei Vladimirescu, Amara Amara, Costin Anghel |