D. Preethi
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2024–2024
Best venue rank
C
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2024 | ISNN | Optimized VLSI Circuit Partitioning and Testing Using ACO and BIST Architectures. | M. R. Ezilarasan, D. Preethi, Man-Fai Leung, Hangjun Che, Xiangguang Dai |