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Daniel Lustig

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

22

Venues

5

Active years

2011–2023

Best venue rank

A*

Where they publish

Papers

22 indexed papers, newest first.

YearVenueTitleAuthors
2023CGOParsimony: Enabling SIMD/Vector Programming in Standard Compiler Flows.Vijay Kandiah, Daniel Lustig, Oreste Villa, David W. Nellans, Nikos Hardavellas
2023HPCAFinePack: Transparently Improving the Efficiency of Fine-Grained Transfers in Multi-GPU Systems.Harini Muthukrishnan, Daniel Lustig, Oreste Villa, Thomas F. Wenisch, David W. Nellans
2022ISCAMixed-proxy extensions for the NVIDIA PTX memory consistency model: industrial product.Daniel Lustig, Simon Cooksey, Olivier Giroux
2021HPCANeed for Speed: Experiences Building a Trustworthy System-Level GPU Simulator.Oreste Villa, Daniel Lustig, Zi Yan, Evgeny Bolotin, Yaosheng Fu, Niladrish Chatterjee, Nan Jiang, David W. Nellans
2021ISCAEfficient Multi-GPU Shared Memory via Automatic Optimization of Fine-Grained Transfers.Harini Muthukrishnan, David W. Nellans, Daniel Lustig, Jeffrey A. Fessler, Thomas F. Wenisch
2021MICROGPS: A Global Publish-Subscribe Model for Multi-GPU Memory Management.Harini Muthukrishnan, Daniel Lustig, David W. Nellans, Thomas F. Wenisch
2020HPCAHMG: Extending Cache Coherence Protocols Across Modern Hierarchical Multi-GPU Systems.Xiaowei Ren, Daniel Lustig, Evgeny Bolotin, Aamer Jaleel, Oreste Villa, David W. Nellans
2019ASPLOSA Formal Analysis of the NVIDIA PTX Memory Consistency Model.Daniel Lustig, Sameer D. Sahasrabuddhe, Olivier Giroux
2019ASPLOSNimble Page Management for Tiered Memory Systems.Zi Yan, Daniel Lustig, David W. Nellans, Abhishek Bhattacharjee
2019ISCATranslation ranger: operating system support for contiguity-aware TLBs.Zi Yan, Daniel Lustig, David W. Nellans, Abhishek Bhattacharjee
2018MICROPipeProof: Automated Memory Consistency Proofs for Microarchitectural Specifications.Yatin A. Manerkar, Daniel Lustig, Margaret Martonosi, Aarti Gupta
2018MICROCheckMate: Automated Synthesis of Hardware Exploits and Security Litmus Tests.Caroline Trippel, Daniel Lustig, Margaret Martonosi
2017ASPLOSAutomated Synthesis of Comprehensive Memory Model Litmus Test Suites.Daniel Lustig, Andrew Wright, Alexandros Papakonstantinou, Olivier Giroux
2017ASPLOSTriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA.Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi
2017MICRORTLcheck: verifying the memory consistency of RTL designs.Yatin A. Manerkar, Daniel Lustig, Margaret Martonosi, Michael Pellauer
2016ASPLOSCOATCheck: Verifying Memory Ordering at the Hardware-OS Interface.Daniel Lustig, Geet Sethi, Margaret Martonosi, Abhishek Bhattacharjee
2015ISCAArMOR: defending against memory consistency model mismatches in heterogeneous architectures.Daniel Lustig, Caroline Trippel, Michael Pellauer, Margaret Martonosi
2015MICROCCICheck: using hb graphs to verify the coherence-consistency interface.Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi
2014MICROPipe Check: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency Models.Daniel Lustig, Michael Pellauer, Margaret Martonosi
2013HPCAReducing GPU offload latency via fine-grained CPU-GPU synchronization.Daniel Lustig, Margaret Martonosi
2013ISCATriggered instructions: a control paradigm for spatially-programmed architectures.Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer
2011HPCAShared last-level TLBs for chip multiprocessors.Abhishek Bhattacharjee, Daniel Lustig, Margaret Martonosi