| 2025 | EDCC | Initial Insights into Synthesis Overheads Caused by C-Based Error Correction Codes Implementations. | Joaquin Gracia-Moran, David de Andrs, Luis J. Saiz-Adalid, Juan Carlos Ruiz, Juan-Carlos Baraza-Calvo, Daniel Gil-Tomas, Pedro J. Gil-Vicente |
| 2025 | EDCC | Towards SW-Based Robustness Assessment of HW Accelerators for Quantized CNNs. | Juan Carlos Ruiz, David de Andrs, Luis J. Saiz-Adalid, Joaquin Gracia-Moran |
| 2025 | EDCC | Towards a Novel 8-Bit Floating-Point Format to Increase Robustness in Convolutional Neural Networks. | Luis J. Saiz-Adalid, Juan-Carlos Ruiz-Garcia, Joaquin Gracia-Moran, David de Andrs, Juan-Carlos Baraza-Calvo, Daniel Gil-Tomas, Pedro J. Gil-Vicente |
| 2025 | SAFECOMP | Can C-Based ECC Models Leverage High-Level Synthesis? Evaluating Description Variants for Efficient Circuit Implementations. | Joaquin Gracia-Moran, Juan-Carlos Ruiz-Garcia, David de Andrs, Luis J. Saiz-Adalid |
| 2024 | EDCC | Zero-Space In-Weight and In-Bias Protection for Floating-Point-based CNNs. | Juan Carlos Ruiz, David de Andrs, Luis J. Saiz-Adalid, Joaquin Gracia-Moran |
| 2024 | SAFECOMP | In-Memory Zero-Space Floating-Point-Based CNN Protection Using Non-significant and Invariant Bits. | Juan Carlos Ruiz, David de Andrs, Luis J. Saiz-Adalid, Joaquin Gracia-Moran |
| 2023 | DATE | BAFFI: a bit-accurate fault injector for improved dependability assessment of FPGA prototypes. | Ilya Tuzov, David de Andrs, Juan-Carlos Ruiz-Garcia, Carles Hernndez |
| 2022 | EDCC | Reversing FPGA architectures for speeding up fault injection: does it pay? | Ilya Tuzov, David de Andrs, Juan Carlos Ruiz |
| 2020 | EDCC | Improving Robustness-Aware Design Space Exploration for FPGA-Based Systems. | Ilya Tuzov, David de Andrs, Juan Carlos Ruiz |
| 2019 | EDCC | Robustness-Aware Design Space Exploration Through Iterative Refinement of D-Optimal Designs. | Ilya Tuzov, David de Andrs, Juan Carlos Ruiz |
| 2018 | DSN | DAVOS: EDA Toolkit for Dependability Assessment, Verification, Optimisation and Selection of Hardware Models. | Ilya Tuzov, David de Andrs, Juan Carlos Ruiz |
| 2018 | EDCC | Accurate Robustness Assessment of HDL Models Through Iterative Statistical Fault Injection. | Ilya Tuzov, David de Andrs, Juan Carlos Ruiz |
| 2017 | DSN | Dependability-Aware Design Space Exploration for Optimal Synthesis Parameters Tuning. | Ilya Tuzov, David de Andrs, Juan Carlos Ruiz |
| 2017 | EDCC | Accurately Simulating the Effects of Faults in VHDL Models Described at the Implementation-Level. | Ilya Tuzov, Juan Carlos Ruiz, David de Andrs |
| 2015 | DAC | Analysis and RTL correlation of instruction set simulators for automotive microcontroller robustness verification. | Jaime Espinosa, Carles Hernndez, Jaume Abella, David de Andrs, Juan-Carlos Ruiz-Garcia |
| 2015 | EDCC | Increasing the Dependability of VLSI Systems through Early Detection of Fugacious Faults. | Jaime Espinosa, David de Andrs, Pedro J. Gil |
| 2014 | EDCC | Gaining Confidence on Dependability Benchmarks' Conclusions through "Back-to-Back" Testing (Practical Experience Report). | Miquel Martnez, David de Andrs, Juan-Carlos Ruiz-Garcia |
| 2013 | AINA | Fault Tolerance on NoCs. | Jos Miguel Montaana, David de Andrs, Francisco Tirado |
| 2013 | SAFECOMP | Preventing Memory Errors in Networked Vehicle Services Through Diversification. | Hector Marco-Gisbert, Juan Carlos Ruiz, David de Andrs, Ismael Ripoll |
| 2012 | DSN | Mitigating the impact of ambient noise on Wireless Mesh Networks using adaptive link-quality-based packet replication. | Jesus Friginal, Juan-Carlos Ruiz-Garcia, David de Andrs, Antonio Bustos |
| 2012 | FPL | Tolerating multiple faults with proximate manifestations in FPGA-based critical designs for harsh environments. | Jaime Espinosa, David de Andrs, Juan Carlos Ruiz, Pedro J. Gil |
| 2011 | NCA | Using Performance, Energy Consumption, and Resilience Experimental Measures to Evaluate Routing Protocols for Ad Hoc Networks. | Jesus Friginal, David de Andrs, Juan-Carlos Ruiz-Garcia, Pedro J. Gil |
| 2011 | PRDC | Using Dependability Benchmarks to Support ISO/IEC SQuaRE. | Jesus Friginal, David de Andrs, Juan-Carlos Ruiz-Garcia, Regina Moraes |
| 2011 | SRDS | Resilience-Driven Parameterisation of Ad Hoc Routing Protocols: olsrd as a Case Study. | Jesus Friginal, David de Andrs, Juan-Carlos Ruiz-Garcia, Pedro J. Gil |
| 2010 | SRDS | Attack Injection to Support the Evaluation of Ad Hoc Networks. | Jesus Friginal, David de Andrs, Juan-Carlos Ruiz-Garcia, Pedro J. Gil |
| 2009 | ETFA | Design and Deployment of a Generic ECC-based Fault Tolerance Mechanism for Embedded HW Cores. | Juan-Carlos Ruiz-Garcia, David de Andrs, Pedro J. Gil |
| 2009 | PRDC | An Attack Injection Approach to Evaluate the Robustness of Ad Hoc Networks. | David de Andrs, Jesus Friginal, Juan-Carlos Ruiz-Garcia, Pedro J. Gil |
| 2008 | EDCC | Dependability Assessment for the Selection of Embedded Cores. | David de Andrs, Juan-Carlos Ruiz-Garcia, Daniel Gil, Pedro J. Gil |
| 2008 | PRDC | Generic Design and Automatic Deployment of NMR Strategies on HW Cores. | Juan-Carlos Ruiz-Garcia, David de Andrs, Sara Blanc, Pedro J. Gil |
| 2006 | DSN | Run-Time Reconfiguration for Emulating Transient Faults in VLSI Systems. | David de Andrs, Juan-Carlos Ruiz-Garcia, Daniel Gil, Pedro J. Gil |
| 2006 | FPL | Fast Emulation of Permanent Faults in VLSI Systems. | David de Andrs, Juan-Carlos Ruiz-Garcia, Daniel Gil, Pedro J. Gil |
| 2005 | EDCC | Fast Run-Time Reconfiguration for SEU Injection. | David de Andrs, Jos Albaladejo, Lenin Lemus, Pedro J. Gil |
| 2003 | DSN | INERTE: Integrated NExus-Based Real-Time Fault Injection Tool for Embedded Systems. | Pedro Yuste, David de Andrs, Lenin Lemus, Juan Jos Serrano, Pedro J. Gil |