David J. Foley
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2000–2000
Best venue rank
C
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2000 | ISCAS | A 3.3 V, 1.6 GHz, low-jitter, self-correcting DLL based clock synthesizer in 0.5 μm CMOS. | David J. Foley, Michael P. Flynn |