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A 3.3 V, 1.6 GHz, low-jitter, self-correcting DLL based clock synthesizer in 0.5 μm CMOS.
David J. Foley
,
Michael P. Flynn
Venue
C
ISCAS
Year
2000
Proceedings
ISCAS
DBLP record
conf/iscas/FoleyF00 ↗
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