Davide Sacchetto
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
4
Active years
2010–2015
Best venue rank
A*
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2015 | DATE | A ultra-low-power FPGA based on monolithically integrated RRAMs. | Pierre-Emmanuel Gaillardon, Xifan Tang, Jury Sandrini, Maxime Thammasack, Somayyeh Rahimian Omam, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli |
| 2015 | ISCAS | Low-voltage read/write circuit design for transistorless ReRAM crossbar arrays in 180nm CMOS technology. | Jury Sandrini, Tugba Demirci, Maxime Thammasack, Davide Sacchetto, Yusuf Leblebici |
| 2013 | DAC | Towards structured ASICs using polarity-tunable Si nanowire transistors. | Pierre-Emmanuel Gaillardon, Michele De Marchi, Luca Gaetano Amar, Shashikanth Bobba, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli |
| 2013 | DATE | Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs. | Pierre-Emmanuel Gaillardon, Luca Gaetano Amar, Shashikanth Bobba, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli |
| 2011 | ICCAD | Alternative design methodologies for the next generation logic switch. | Davide Sacchetto, Michele De Marchi, Giovanni De Micheli, Yusuf Leblebici |
| 2010 | ISCAS | Memristive devices fabricated with silicon nanowire schottky barrier transistors. | Davide Sacchetto, M. Haykel Ben Jamaa, Sandro Carrara, Giovanni De Micheli, Yusuf Leblebici |
| 2010 | ISCAS | Design aspects of carry lookahead adders with vertically-stacked nanowire transistors. | Davide Sacchetto, M. Haykel Ben Jamaa, Giovanni De Micheli, Yusuf Leblebici |