Skip to content

Dean M. Tullsen

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

95

Venues

21

Active years

1993–2025

Best venue rank

A*

Where they publish

Papers

95 indexed papers, newest first.

YearVenueTitleAuthors
2025ASPLOSExtended User Interrupts (xUI): Fast and Flexible Notification without Polling.Berk Aydogmus, Linsong Guo, Danial Zuberi, Tal Garfinkel, Dean M. Tullsen, Amy Ousterhout, Kazem Taram
2025ASPLOSSegue & ColorGuard: Optimizing SFI Performance and Scalability on Modern Architectures.Shravan Narayan, Tal Garfinkel, Evan Johnson, Zachary Yedidia, Yingchen Wang, Andrew Brown, Anjo Vahldiek-Oberwagner, Michael LeMay, Wenyong Huang, Xin Wang, Mingqiu Sun, Dean M. Tullsen, Deian Stefan
2024ASPLOSPDIP: Priority Directed Instruction Prefetching.Bhargav Reddy Godala, Sankara Prasad Ramesh, Gilles A. Pokam, Jared Stark, Andr Seznec, Dean M. Tullsen, David I. August
2024ASPLOSPathfinder: High-Resolution Control-Flow Attacks Exploiting the Conditional Branch Predictor.Hosein Yavarzadeh, Archit Agarwal, Max Christman, Christina Garman, Daniel Genkin, Andrew Kwong, Daniel Moghimi, Deian Stefan, Kazem Taram, Dean M. Tullsen
2023ASPLOSGoing beyond the Limits of SFI: Flexible and Secure Hardware-Assisted In-Process Isolation with HFI.Shravan Narayan, Tal Garfinkel, Mohammadkazem Taram, Joey Rudek, Daniel Moghimi, Evan Johnson, Chris Fallin, Anjo Vahldiek-Oberwagner, Michael LeMay, Ravi Sahita, Dean M. Tullsen, Deian Stefan
2023SPHalf&Half: Demystifying Intel's Directional Branch Predictors for Fast, Secure Partitioned Execution.Hosein Yavarzadeh, Mohammadkazem Taram, Shravan Narayan, Deian Stefan, Dean M. Tullsen
2023SPHalf&Half: Demystifying Intel's Directional Branch Predictors for Fast, Secure Partitioned Execution.Hosein Yavarzadeh, Mohammadkazem Taram, Shravan Narayan, Deian Stefan, Dean M. Tullsen
2022MICROEVAX: Towards a Practical, Pro-active & Adaptive Architecture for High Performance & Security.Samira Mirbagher Ajorpaz, Daniel Moghimi, Jeffrey Neal Collins, Gilles Pokam, Nael B. Abu-Ghazaleh, Dean M. Tullsen
2021ISCAI See Dead ops: Leaking Secrets via Intel/AMD Micro-Op Caches.Xida Ren, Logan Moody, Mohammadkazem Taram, Matthew Jordan, Dean M. Tullsen, Ashish Venkat
2021WWWNot All Features Are Equal: Discovering Essential Features for Preserving Prediction Privacy.Fatemehsadat Mireshghallah, Mohammadkazem Taram, Ali Jalali, Ahmed Taha Elthakeb, Dean M. Tullsen, Hadi Esmaeilzadeh
2020ASPLOSShredder: Learning Noise Distributions to Protect Inference Privacy.Fatemehsadat Mireshghallah, Mohammadkazem Taram, Prakash Ramrakhyani, Ali Jalali, Dean M. Tullsen, Hadi Esmaeilzadeh
2020ISCAPacket Chasing: Spying on Network Packets over a Cache Side-Channel.Mohammadkazem Taram, Ashish Venkat, Dean M. Tullsen
2020PLDIConstant-time foundations for the new spectre era.Sunjay Cauligi, Craig Disselkoen, Klaus von Gleissenthall, Dean M. Tullsen, Deian Stefan, Tamara Rezk, Gilles Barthe
2019ASPLOSContext-Sensitive Fencing: Securing Speculative Execution via Microcode Customization.Mohammadkazem Taram, Ashish Venkat, Dean M. Tullsen
2019HPCAUnderstanding the Impact of Socket Density in Density Optimized Servers.Manish Arora, Matt Skach, Wei Huang, Xudong An, Jason Mars, Lingjia Tang, Dean M. Tullsen
2019HPCAComposite-ISA Cores: Enabling Multi-ISA Heterogeneity Using a Single ISA.Ashish Venkat, Harsha Basavaraj, Dean M. Tullsen
2019PPoPPDeciphering Predictive Schedulers for Heterogeneous-ISA Multicore Architectures.Andreas Prodromou, Ashish Venkat, Dean M. Tullsen
2018HPCAReliability-Aware Data Placement for Heterogeneous Memory Architecture.Manish Gupta, Vilas Sridharan, David Roberts, Andreas Prodromou, Ashish Venkat, Dean M. Tullsen, Rajesh K. Gupta
2018ISCAVirtual Melting Temperature: Managing Server Load to Minimize Cooling Overhead with Phase Change Materials.Matt Skach, Manish Arora, Dean M. Tullsen, Lingjia Tang, Jason Mars
2018ISCAMobilizing the Micro-Ops: Exploiting Context Sensitive Decoding for Security and Energy Efficiency.Mohammadkazem Taram, Ashish Venkat, Dean M. Tullsen
2017DACCompiler Techniques to Reduce the Synchronization Overhead of GPU Redundant Multithreading.Manish Gupta, Daniel Lowell, John Kalamatianos, Steven Raasch, Vilas Sridharan, Dean M. Tullsen, Rajesh K. Gupta
2017HPCAMemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level Memories.Andreas Prodromou, Mitesh R. Meswani, Nuwan Jayasena, Gabriel H. Loh, Dean M. Tullsen
2016ASPLOSHIPStR: Heterogeneous-ISA Program State Relocation.Ashish Venkat, Sriskanda Shamasunder, Hovav Shacham, Dean M. Tullsen
2016USENIXHorton Tables: Fast Hash Tables for In-Memory Data-Intensive Computing.Alex D. Breslow, Dong Ping Zhang, Joseph L. Greathouse, Nuwan Jayasena, Dean M. Tullsen
2015HPCAUnderstanding idle behavior and power gating mechanisms in the context of modern benchmarks on CPU-GPU Integrated systems.Manish Arora, Srilatha Manne, Indrani Paul, Nuwan Jayasena, Dean M. Tullsen
2015ISCAThermal time shifting: leveraging phase change materials to reduce cooling costs in warehouse-scale computers.Matt Skach, Manish Arora, Chang-Hong Hsu, Qi Li, Dean M. Tullsen, Lingjia Tang, Jason Mars
2015MICROThe CRISP performance model for dynamic voltage and frequency scaling in a GPGPU.Rajib Nath, Dean M. Tullsen
2014DACEnabling Dynamic Heterogeneity Through Core-on-Core Stacking.Vasileios Kontorinis, Mohammad Khavari Tavana, Mohammad Hossein Hajkazemi, Dean M. Tullsen, Houman Homayoun
2014HPCACDTT: Compiler-generated data-triggered threads.Hung-Wei Tseng, Dean M. Tullsen
2014ICCDModeling and analysis of Phase Change Materials for efficient thermal management.Fulya Kaplan, Charlie De Vivero, Samuel Howes, Manish Arora, Houman Homayoun, Wayne P. Burleson, Dean M. Tullsen, Ayse K. Coskun
2014ISCAHarnessing ISA diversity: Design of a heterogeneous-ISA chip multiprocessor.Ashish Venkat, Dean M. Tullsen
2014SIGMETRICSA comparison of core power gating strategies implemented in modern hardware.Manish Arora, Srilatha Manne, Yasuko Eckert, Indrani Paul, Nuwan Jayasena, Dean M. Tullsen
2013ICCDLow-current probabilistic writes for power-efficient STT-RAM caches.Nikolaos Strikos, Vasileios Kontorinis, Xiangyu Dong, Houman Homayoun, Dean M. Tullsen
2013SCLoad-balanced pipeline parallelism.Md. Kamruzzaman, Steven Swanson, Dean M. Tullsen
2012ASPLOSExecution migration in a heterogeneous-ISA chip multiprocessor.Matthew DeVuyst, Ashish Venkat, Dean M. Tullsen
2012EuroParThemis: Energy Efficient Management of Workloads in Virtualized Data Centers.Gaurav Dhiman, Vasileios Kontorinis, Raid Zuhair Ayoub, Liuyi Eric Zhang, Chris Sadler, Dean M. Tullsen, Tajana Simunic Rosing
2012HPCADynamically heterogeneous cores through 3D resource pooling.Houman Homayoun, Vasileios Kontorinis, Amirali Shayan, Ta-Wei Lin, Dean M. Tullsen
2012ICCDRetrospective on "Power-Sensitive Multithreaded Architecture".John S. Seng, Dean M. Tullsen, George Z. N. Cai
2012ICCDPower-sensitive multithreaded architecture.John S. Seng, Dean M. Tullsen, George Z. N. Cai
2012ISCAManaging distributed UPS energy for effective power capping in data centers.Vasileios Kontorinis, Liuyi Eric Zhang, Baris Aksanli, Jack Sampson, Houman Homayoun, Eddie Pettis, Dean M. Tullsen, Tajana Simunic Rosing
2012OOPSLASoftware data-triggered threads.Hung-Wei Tseng, Dean M. Tullsen
2012SIGMETRICSFast cost efficient designs by building upon the plackett and burman method.Manish Arora, Feng Wang, Bob Rychlik, Dean M. Tullsen
2011ASPLOSInter-core prefetching for multicore processors using migrating helper threads.Md. Kamruzzaman, Steven Swanson, Dean M. Tullsen
2011HPCAFast thread migration via cache working set prediction.Jeffery A. Brown, Leo Porter, Dean M. Tullsen
2011HPCAData-triggered threads: Eliminating redundant computation.Hung-Wei Tseng, Dean M. Tullsen
2010ICCDInter-socket victim cacheing for platform power reduction.Subhra Mazumdar, Dean M. Tullsen, Justin J. Song
2010ISLPEDDynamic workload characterization for power efficient scheduling on CMP systems.Gaurav Dhiman, Vasileios Kontorinis, Dean M. Tullsen, Tajana Rosing, Eric Saxe, Jonathan Chew
2010PLDISoftware data spreading: leveraging distributed caches to improve single thread performance.Md. Kamruzzaman, Steven Swanson, Dean M. Tullsen
2009ICSCreating artificial global history to improve branch prediction accuracy.Leo Porter, Dean M. Tullsen
2009MICROReducing peak power with a table-driven adaptive processor core.Vasileios Kontorinis, Amirali Shayan, Dean M. Tullsen, Rakesh Kumar
2009MICROMcPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures.Sheng Li, Jung Ho Ahn, Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, Norman P. Jouppi
2009SIGMETRICSEvaluating the impact of job scheduling and power management on processor lifetime for chip multiprocessors.Ayse K. Coskun, Richard D. Strong, Dean M. Tullsen, Tajana Simunic Rosing
2008ASPLOSAccurate branch prediction for short threads.Bumyong Choi, Leo Porter, Dean M. Tullsen
2008ICSThe shared-thread multiprocessor.Jeffery A. Brown, Dean M. Tullsen
2008ISPDCHolistic Design of Multiple-Core Architectures.Dean M. Tullsen
2007HPCAAccelerating and Adapting Precomputation Threads for Effcient Prefetching.Weifeng Zhang, Dean M. Tullsen, Brad Calder
2007SPAAProximity-aware directory-based coherence for multi-core processor architectures.Jeffery A. Brown, Rakesh Kumar, Dean M. Tullsen
2006CGOA Self-Repairing Prefetcher in an Event-Driven Dynamic Optimization Framework.Weifeng Zhang, Brad Calder, Dean M. Tullsen
2006ICCADApplication-specific customization of parameterized FPGA soft-core processors.David Sheldon, Rakesh Kumar, Roman L. Lysecky, Frank Vahid, Dean M. Tullsen
2006ICCADConjoining soft-core FPGA processors.David Sheldon, Rakesh Kumar, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky
2006ICCDSpeculative Code Value Specialization Using the Trace Cache Fill Unit.Weifeng Zhang, Brad Calder, Dean M. Tullsen, Steve Checkoway
2005HPCAMultithreaded Value Prediction.Nathan Tuck, Dean M. Tullsen
2005ISCAA Tree Based Router Search Engine Architecture with Single Port Memories.Florin Baboescu, Dean M. Tullsen, Grigore Rosu, Sumeet Singh
2005ISCAInterconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling.Rakesh Kumar, Victor V. Zyuban, Dean M. Tullsen
2005PLDIMitosis compiler: an infrastructure for speculative threading based on pre-computation slices.Carlos Garca Quiones, Carlos Madriles, F. Jess Snchez, Pedro Marcuello, Antonio Gonzlez, Dean M. Tullsen
2004ISCASingle-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance.Rakesh Kumar, Dean M. Tullsen, Parthasarathy Ranganathan, Norman P. Jouppi, Keith I. Farkas
2004MICROControl Flow Optimization Via Dynamic Reconvergence Prediction.Jamison D. Collins, Dean M. Tullsen, Hong Wang
2004MICROConjoined-Core Chip Multiprocessing.Rakesh Kumar, Norman P. Jouppi, Dean M. Tullsen
2004MICROBalanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy.Eric Tune, Rakesh Kumar, Dean M. Tullsen, Brad Calder
2003MICROSingle-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction.Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen
2002MICROPointer cache assisted prefetching.Jamison D. Collins, Suleyman Sair, Brad Calder, Dean M. Tullsen
2002MICROCompiling for instruction cache performance on a multithreaded architecture.Rakesh Kumar, Dean M. Tullsen
2002SIGMETRICSSymbiotic jobscheduling with priorities for a simultaneous multithreading processor.Allan Snavely, Dean M. Tullsen, Geoffrey M. Voelker
2001HPCADynamic Prediction of Critical Path Instructions.Eric Tune, Dongning Liang, Dean M. Tullsen, Brad Calder
2001ISCASpeculative precomputation: long-range prefetching of delinquent loads.Jamison D. Collins, Hong Wang, Dean M. Tullsen, Christopher J. Hughes, Yong-Fong Lee, Daniel M. Lavery, John Paul Shen
2001MICRODynamic speculative precomputation.Jamison D. Collins, Dean M. Tullsen, Hong Wang, John Paul Shen
2001MICROReducing power with dynamic critical path information.John S. Seng, Eric Tune, Dean M. Tullsen
2001MICROHandling long-latency loads in a simultaneous multithreading processor.Dean M. Tullsen, Jeffery A. Brown
2000ASPLOSSymbiotic Jobscheduling for a Simultaneous Multithreading Processor.Allan Snavely, Dean M. Tullsen
2000ICCDPower-Sensitive Multithreaded Architecture.John S. Seng, Dean M. Tullsen, George Z. N. Cai
1999HPCAMultithreaded Execution Architecture and Compilation.Dean M. Tullsen, Guang R. Gao
1999HPCASupporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor.Dean M. Tullsen, Jack L. Lo, Susan J. Eggers, Henry M. Levy
1999HPCAInstruction Recycling on a Multiple-Path Processor.Steven Wallace, Dean M. Tullsen, Brad Calder
1999ISCASelective Value Prediction.Brad Calder, Glenn Reinman, Dean M. Tullsen
1999ISCAStorageless Value Prediction Using Prior Register Values.Dean M. Tullsen, John S. Seng
1999ICSClassifying load and store instructions for memory renaming.Glenn Reinman, Brad Calder, Dean M. Tullsen, Gary S. Tyson, Todd M. Austin
1999MICROHardware Identification of Cache Conflict Misses.Jamison D. Collins, Dean M. Tullsen
1999SCILP versus TLP on SMT.Nicholas Mitchell, Larry Carter, Jeanne Ferrante, Dean M. Tullsen
1998ISCARetrospective: Simultaneous Multithreading: Maximizing On-Chip Parallelism.Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
1998ISCASimultaneous Multithreading: Maximizing On-Chip Parallelism.Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
1998ISCAThreaded Multiple Path Execution.Steven Wallace, Brad Calder, Dean M. Tullsen
1997MICROTuning Compiler Optimizations for Simultaneous Multithreading.Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay S. Parekh, Dean M. Tullsen
1996ISCAExploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor.Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm
1995ISCASimultaneous Multithreading: Maximizing On-Chip Parallelism.Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
1993ISCALimitations of Cache Prefetching on a Bus-Based Multiprocessor.Dean M. Tullsen, Susan J. Eggers