Dilip P. Vasudevan
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
3
Active years
2008–2019
Best venue rank
C
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2019 | ISPASS | PARADISE - Post-Moore Architecture and Accelerator Design Space Exploration Using Device Level Simulation and Experiments. | Dilip P. Vasudevan, George Michelogiannakis, David Donofrio, John Shalf |
| 2011 | DSD | Design of a Low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit Using a Bidirectional Adder. | Jiaoyan Chen, Dilip P. Vasudevan, Emanuel M. Popovici, Michel P. Schellekens |
| 2010 | DSD | Static Average Case Power Estimation Technique for Block Ciphers. | Tingcong Ye, Dilip P. Vasudevan, Jiaoyan Chen, Emanuel M. Popovici, Michel P. Schellekens |
| 2008 | DDECS | A Partial Scan Based Test Generation for Asynchronous Circuits. | Dilip P. Vasudevan, Aristides Efthymiou |