Dimin Niu
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
39
Venues
14
Active years
2010–2025
Best venue rank
A*
Where they publish
Papers
39 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ASPLOS | CTXNL: A Software-Hardware Co-designed Solution for Efficient CXL-Based Transaction Processing. | Zhao Wang, Yiqi Chen, Cong Li, Yijin Guan, Dimin Niu, Tianchan Guan, Zhaoyang Du, Xingda Wei, Guangyu Sun |
| 2025 | CVPR | Frequency-Biased Synergistic Design for Image Compression and Compensation. | Jiaming Liu, Qi Zheng, Zihao Liu, Yilian Zhong, Peiye Liu, Tao Liu, Shusong Xu, Yanheng Lu, Sicheng Li, Dimin Niu, Yibo Fan |
| 2025 | ICCAD | HD-MoE: Hybrid and Dynamic Parallelism for Mixture-of-Expert LLMs with 3D Near-Memory Processing. | Haochen Huang, Shuzhang Zhong, Zhe Zhang, Shuangchen Li, Dimin Niu, Hongzhong Zheng, Runsheng Wang, Meng Li |
| 2025 | ISCA | H | Cong Li, Yihan Yin, Xintong Wu, Jingchen Zhu, Zhutianya Gao, Dimin Niu, Qiang Wu, Xin Si, Yuan Xie, Chen Zhang, Guangyu Sun |
| 2024 | ASPLOS | Salus: A Practical Trusted Execution Environment for CPU-FPGA Heterogeneous Cloud Platforms. | Yu Zou, Yiran Li, Sheng Wang, Le Su, Zhen Gu, Yanheng Lu, Yijin Guan, Dimin Niu, Mingyu Gao, Yuan Xie, Feifei Li |
| 2024 | CVPR | Zero-Shot Structure-Preserving Diffusion Model for High Dynamic Range Tone Mapping. | Ruoxi Zhu, Shusong Xu, Peiye Liu, Sicheng Li, Yanheng Lu, Dimin Niu, Zihao Liu, Zihao Meng, Zhiyong Li, Xinhua Chen, Yibo Fan |
| 2024 | USENIX | HydraRPC: RPC in the CXL Era. | Teng Ma, Zheng Liu, Chengkun Wei, Jialiang Huang, Youwei Zhuo, Haoyu Li, Ning Zhang, Yijin Guan, Dimin Niu, Mingxing Zhang, Tao Ma |
| 2023 | ASPLOS | Spada: Accelerating Sparse Matrix Multiplication with Adaptive Dataflow. | Zhiyao Li, Jiaxiang Li, Taijie Chen, Dimin Niu, Hongzhong Zheng, Yuan Xie, Mingyu Gao |
| 2023 | DAC | NMExplorer: An Efficient Exploration Framework for DIMM-based Near-Memory Tensor Reduction. | Cong Li, Zhe Zhou, Xingchen Li, Guangyu Sun, Dimin Niu |
| 2023 | DAC | CHAM: A Customized Homomorphic Encryption Accelerator for Fast Matrix-Vector Product. | Xuanle Ren, Zhaohui Chen, Zhen Gu, Yanheng Lu, Ruiguang Zhong, Wen-Jie Lu, Jiansong Zhang, Yichi Zhang, Hanghang Wu, Xiaofu Zheng, Heng Liu, Tingqiang Chu, Cheng Hong, Changzheng Wei, Dimin Niu, Yuan Xie |
| 2023 | MICRO | TT-GNN: Efficient On-Chip Graph Neural Network Training via Embedding Reformation and Hardware Optimization. | Zheng Qu, Dimin Niu, Shuangchen Li, Hongzhong Zheng, Yuan Xie |
| 2022 | HPCA | Enabling High-Quality Uncertainty Quantification in a PIM Designed for Bayesian Neural Network. | Xingchen Li, Bingzhe Wu, Guangyu Sun, Zhe Zhang, Zhihang Yuan, Runsheng Wang, Ru Huang, Dimin Niu, Hongzhong Zheng, Zhichao Lu, Liang Zhao, Meng-Fan Marvin Chang, Tianchan Guan, Xin Si |
| 2022 | ICPADS | Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio. | Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Nianxiong Tan, Xiaopeng Yu, Hongzhong Zheng, Jianyi Meng, Xiaolang Yan, Yuan Xie |
| 2022 | ISCA | Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network. | Shuangchen Li, Dimin Niu, Yuhao Wang, Wei Han, Zhe Zhang, Tianchan Guan, Yijin Guan, Heng Liu, Linyong Huang, Zhaoyang Du, Fei Xue, Yuanwei Fang, Hongzhong Zheng, Yuan Xie |
| 2020 | ISCA | iPIM: Programmable In-Memory Image Processing Accelerator Using Near-Bank Architecture. | Peng Gu, Xinfeng Xie, Yufei Ding, Guoyang Chen, Weifeng Zhang, Dimin Niu, Yuan Xie |
| 2019 | MICRO | GraphQ: Scalable PIM-Based Graph Processing. | Youwei Zhuo, Chao Wang, Mingxing Zhang, Rui Wang, Dimin Niu, Yanzhi Wang, Xuehai Qian |
| 2018 | MICRO | SCOPE: A Stochastic Computing Engine for DRAM-Based In-Situ Accelerator. | Shuangchen Li, Alvin Oliver Glova, Xing Hu, Peng Gu, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Yuan Xie |
| 2017 | MICRO | DRISA: a DRAM-based reconfigurable in-situ accelerator. | Shuangchen Li, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Yuan Xie |
| 2016 | ISCA | DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric. | Mingyu Gao, Christina Delimitrou, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Christos Kozyrakis |
| 2015 | HPCA | Overcoming the challenges of crossbar resistive memory architectures. | Cong Xu, Dimin Niu, Naveen Muralimanohar, Rajeev Balasubramonian, Tao Zhang, Shimeng Yu, Yuan Xie |
| 2014 | ASPDAC | Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architecture. | Cong Xu, Dimin Niu, Shimeng Yu, Yuan Xie |
| 2014 | ASPDAC | 3DLAT: TSV-based 3D ICs crosstalk minimization utilizing Less Adjacent Transition code. | Qiaosha Zou, Dimin Niu, Yan Cao, Yuan Xie |
| 2014 | ICCAD | Architecting 3D vertical resistive memory for next-generation storage systems. | Cong Xu, Pai-Yu Chen, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie |
| 2014 | ISLPED | SBAC: a statistics based cache bypassing method for asymmetric-access caches. | Chao Zhang, Guangyu Sun, Peng Li, Tao Wang, Dimin Niu, Yiran Chen |
| 2013 | DAC | Understanding the trade-offs in multi-level cell ReRAM memory design. | Cong Xu, Dimin Niu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie |
| 2013 | ICCAD | Design of cross-point metal-oxide ReRAM emphasizing reliability and cost. | Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie |
| 2013 | ICCD | Low power multi-level-cell resistive memory design with incomplete data mapping. | Dimin Niu, Qiaosha Zou, Cong Xu, Yuan Xie |
| 2012 | ASPDAC | Low power memristor-based ReRAM design with Error Correcting Code. | Dimin Niu, Yang Xiao, Yuan Xie |
| 2012 | ISLPED | Design trade-offs for high density cross-point resistive memory. | Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie |
| 2011 | ASPDAC | A frequent-value based PRAM memory architecture. | Guangyu Sun, Dimin Niu, Jin Ouyang, Yuan Xie |
| 2011 | ICCAD | Device-architecture co-optimization of STT-RAM based memory for low power embedded systems. | Cong Xu, Dimin Niu, Xiaochun Zhu, Seung-Hyuk Kang, Matt Nowak, Yuan Xie |
| 2011 | ICCD | Energy-efficient multi-level cell phase-change memory system with data encoding. | Jue Wang, Xiangyu Dong, Guangyu Sun, Dimin Niu, Yuan Xie |
| 2011 | ICS | F | Jin Ouyang, Chuan Yang, Dimin Niu, Yuan Xie, Zhiwen Liu |
| 2010 | ASPDAC | Energy and performance driven circuit design for emerging phase-change memory. | Dimin Niu, Yibo Chen, Xiangyu Dong, Yuan Xie |
| 2010 | DAC | Impact of process variations on emerging memristor. | Dimin Niu, Yiran Chen, Cong Xu, Yuan Xie |
| 2010 | DATE | Energy- and endurance-aware design of phase change memory caches. | Yongsoo Joo, Dimin Niu, Xiangyu Dong, Guangyu Sun, Naehyuck Chang, Yuan Xie |
| 2010 | HPCA | A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement. | Guangyu Sun, Yongsoo Joo, Yibo Chen, Dimin Niu, Yuan Xie, Yiran Chen, Hai Li |
| 2010 | ICCAD | Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis. | Yibo Chen, Dimin Niu, Yuan Xie, Krishnendu Chakrabarty |
| 2010 | ISLPED | Low-power dual-element memristor based memory design. | Dimin Niu, Yiran Chen, Yuan Xie |