| 2010 | ASPDAC | Resilient design in scaled CMOS for energy efficiency. | James W. Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep P. Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De |
| 2010 | ISCA | Reducing cache power with low-cost, multi-bit error-correcting codes. | Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Wei Wu, Dinesh Somasekhar, Shih-Lien Lu |
| 2006 | ISCAS | Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches. | Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Vivek De |
| 2000 | DAC | Dynamic noise analysis in precharge-evaluate circuits. | Dinesh Somasekhar, Seung Hoon Choi, Kaushik Roy, Yibin Ye, Vivek De |
| 2000 | ICCD | Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family. | Alexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh, Dinesh Somasekhar |
| 1999 | DAC | Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS. | Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy |
| 1999 | ICCD | Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power Design. | Khurram Muhammad, Dinesh Somasekhar, Kaushik Roy |
| 1997 | ISLPED | LVDCSL: low voltage differential current switch logic, a robust low power DCSL family. | Dinesh Somasekhar, Kaushik Roy |
| 1993 | VLSID | A 230MHz Half Bit Level Pipelined Multiplier Using True Single Phase Clocking. | Dinesh Somasekhar, V. Visvanathan |