| 2017 | ATVA | SamaTulyata: An Efficient Path Based Equivalence Checking Tool. | Soumyadip Bandyopadhyay, Santonu Sarkar, Dipankar Sarkar, Chittaranjan A. Mandal |
| 2017 | ATVA | An Equivalence Checking Framework for Array-Intensive Programs. | Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar |
| 2016 | ENASE | An Enhanced Equivalence Checking Method to Handle Bugs in Programs with Recurrences. | Sudakshina Dutta, Dipankar Sarkar |
| 2016 | ENASE | Validation of Loop Parallelization and Loop Vectorization Transformations. | Sudakshina Dutta, Dipankar Sarkar, Arvind Rawat, Kulwant Singh |
| 2015 | ICSE | Poster: An Efficient Equivalence Checking Method for Petri Net Based Models of Programs. | Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal |
| 2015 | ICSoft | A Path-based Equivalence Checking Method for Petri Net based Models of Programs. | Soumyadip Bandyopadhyay, Dipankar Sarkar, Kunal Banerjee, Chittaranjan A. Mandal |
| 2015 | SCAM | A translation validation framework for symbolic value propagation based equivalence checking of FSMDAs. | Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar |
| 2013 | VLSID | Verification of KPN Level Transformations. | Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal |
| 2006 | DDECS | Concurrent Testing of Digital Circuits for Advanced Fault Models. | Santosh Biswas, Siddhartha Mukhopadhyay, P. Patra, Dipankar Sarkar |
| 2004 | ASPDAC | Model checking on state transition diagram. | Batsayan Das, Dipankar Sarkar, Santanu Chattopadhyay |
| 2002 | VLSID | Register Transfer Operation Analysis during Data Path Verification. | Dipankar Sarkar |
| 2000 | VLSID | Status Condition Analysis during Data Path Verification of Sequential Circuits. | Dipankar Sarkar |
| 1997 | VLSID | Inductive Verification of Sequential Circuits with a Datapath. | I. Chakrabarti, Dipankar Sarkar, Arun K. Majumdar |
| 1994 | VLSID | Mechanical Identification of Inductive Properties During Verification of Finite State Machines. | I. Chakrabarti, Dipankar Sarkar |