Skip to content

Dmitry Ponomarev

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

41

Venues

18

Active years

2001–2024

Best venue rank

A*

Where they publish

Papers

41 indexed papers, newest first.

YearVenueTitleAuthors
2024NDSSTEE-SHirT: Scalable Leakage-Free Cache Hierarchies for TEEs.Kerem Arikan, Abraham Farrell, Williams Zhang Cen, Jack McMahon, Barry Williams, Yu David Liu, Nael B. Abu-Ghazaleh, Dmitry Ponomarev
2021ICPPGVT-Guided Demand-Driven Scheduling in Parallel Discrete Event Simulation.Ali Eker, David Timmerman, Barry Williams, Kenneth Chiu, Dmitry Ponomarev
2021PADSLoad-Aware Dynamic Time Synchronization in Parallel Discrete Event Simulation.Ali Eker, Yehia Arafa, Abdel-Hameed A. Badawy, Nandakishore Santhi, Stephan J. Eidenbenz, Dmitry Ponomarev
2021PADSHigh-Performance PDES on Manycore Clusters.Barry Williams, Ali Eker, Kenneth Chiu, Dmitry Ponomarev
2020PADSDemand-Driven PDES: Exploiting Locality in Simulation Models.Ali Eker, Barry Williams, Kenneth Chiu, Dmitry Ponomarev
2019DACSafeSpec: Banishing the Spectre of a Meltdown with Leakage-Free Speculation.Khaled N. Khasawneh, Esmaeil Mohammadian Koruyeh, Chengyu Song, Dmitry Evtyushkin, Dmitry Ponomarev, Nael B. Abu-Ghazaleh
2019ICPPControlled Asynchronous GVT: Accelerating Parallel Discrete Event Simulation on Many-Core Clusters.Ali Eker, Barry Williams, Kenneth Chiu, Dmitry Ponomarev
2019ISCAEA-PLRU: Enclave-Aware Cache Replacement.Atsuko Shimizu, Daniel Townley, Mohit Joshi, Dmitry Ponomarev
2019MICROLATCH: A Locality-Aware Taint CHecker.Daniel Townley, Khaled N. Khasawneh, Dmitry Ponomarev, Nael B. Abu-Ghazaleh, Lei Yu
2018ASPLOSBranchScope: A New Side-Channel Attack on Directional Branch Predictor.Dmitry Evtyushkin, Ryan Riley, Nael B. Abu-Ghazaleh, Dmitry Ponomarev
2017ICCADHardening extended memory access control schemes with self-verified address spaces.Jesse Elwell, Dmitry Evtyushkin, Dmitry Ponomarev, Nael B. Abu-Ghazaleh, Ryan Riley
2017MICRORHMD: evasion-resilient hardware malware detectors.Khaled N. Khasawneh, Nael B. Abu-Ghazaleh, Dmitry Ponomarev, Lei Yu
2017PADSPerformance Characterization of Parallel Discrete Event Simulation on Knights Landing Processor.Barry Williams, Dmitry Ponomarev, Nael B. Abu-Ghazaleh, Philip A. Wilsey
2014HPCAA Non-Inclusive Memory Permissions architecture for protection against cross-layer attacks.Jesse Elwell, Ryan Riley, Nael B. Abu-Ghazaleh, Dmitry Ponomarev
2013HPCASCRAP: Architecture for signature-based protection from Code Reuse Attacks.Mehmet Kayaalp, Timothy Schmitt, Junaid Nomani, Dmitry Ponomarev, Nael B. Abu-Ghazaleh
2013PACTPowerVisor: A Toolset for Visualizing Energy Consumption and Heat Dissipation Processes in Modern Processor Architectures.Alexey Baranov, Peter Panfilov, Dmitry Ponomarev
2013PADSInterference resilient PDES on multi-core systems: towards proportional slowdown.Jingjing Wang, Nael B. Abu-Ghazaleh, Dmitry Ponomarev
2013PADSCan PDES scale in environments with heterogeneous delays?Jingjing Wang, Ketan Bahulkar, Dmitry Ponomarev, Nael B. Abu-Ghazaleh
2012ISCABranch regulation: Low-overhead protection from code reuse attacks.Mehmet Kayaalp, Meltem Ozsoy, Nael B. Abu-Ghazaleh, Dmitry Ponomarev
2011ASPDACMathematical limits of parallel computation for embedded systems.Jason Loew, Jesse Elwell, Dmitry Ponomarev, Patrick H. Madden
2011DACTPM-SIM: a framework for performance evaluation of trusted platform modules.Jared Schmitz, Jason Loew, Jesse Elwell, Dmitry Ponomarev, Nael B. Abu-Ghazaleh
2011PACTCacheVisor: A Toolset for Visualizing Shared Caches in Multicore and Multithreaded Processors.Dmitry Evtyushkin, Peter Panfilov, Dmitry Ponomarev
2010ICCDA co-processor approach for accelerating data-structure intensive algorithms.Jason Loew, Jesse Elwell, Dmitry Ponomarev, Patrick H. Madden
2009ICPPRegister Versioning: A Low-Complexity Implementation of Register Renaming in Out-of-Order Microarchitectures.Hui Zeng, Kanad Ghose, Dmitry Ponomarev
2009ISLPEDEnergy-efficient renaming with register versioning.Hui Zeng, Ju-Young Jung, Kanad Ghose, Dmitry Ponomarev
2008CAINENew Architecture and Protocols for Global-Scale Machine Communities.Vladimir Krylov, N. Mikhaylov, Dmitry Ponomarev
2008CAINEActive Database Architecture for XML Documents.Vladimir Krylov, Dmitry Ponomarev, Andrey Logvinov, Alexander Ponomarenko
2008ICPPTwo-Level Reorder Buffers: Accelerating Memory-Bound Applications on SMT Architectures.Jason Loew, Dmitry Ponomarev
2008SBAC-PADAggressive Scheduling and Speculation in Multithreaded Architectures: Is it Worth its Salt?Jason Loew, Dmitry Ponomarev
2006ICPPAddress-Value Decoupling for Early Register Deallocation.Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Aneesh Aggarwal
2006ICPPBalancing ILP and TLP in SMT Architectures through Out-of-Order Instruction Dispatch.Joseph J. Sharkey, Dmitry Ponomarev
2006ISLPEDSelective writeback: exploiting transient values for energy-efficiency and performance.Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose
2003ICCDDistributed Reorder Buffer Schemes for Low Power.Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose
2003ISLPEDReducing reorder buffer complexity through selective operand caching.Gurhan Kucuk, Dmitry Ponomarev, Oguz Ergin, Kanad Ghose
2003ISLPEDPower efficient comparators for long arguments in superscalar processors.Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose
2002DATEAccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors.Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose
2002ICCDA Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors.Oguz Ergin, Kanad Ghose, Gurhan Kucuk, Dmitry Ponomarev
2002ICSLow-complexity reorder buffer architecture.Gurhan Kucuk, Dmitry Ponomarev, Kanad Ghose
2001EuroParOptimal Polling for Latency-Throughput Tradeoffs in Queue-Based Network Interfaces for Clusters.Dmitry Ponomarev, Kanad Ghose, Evgeny Saksonov
2001ISLPEDEnergy: efficient instruction dispatch buffer design for superscalar processors.Gurhan Kucuk, Kanad Ghose, Dmitry Ponomarev, Peter M. Kogge
2001MICROReducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources.Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose