| 2017 | DAC | RIC: Relaxed Inclusion Caches for Mitigating LLC Side-Channel Attacks. | Mehmet Kayaalp, Khaled N. Khasawneh, Hodjat Asghari Esfeden, Jesse Elwell, Nael B. Abu-Ghazaleh, Dmitry V. Ponomarev, Aamer Jaleel |
| 2016 | CCS | Covert Channels through Random Number Generator: Mechanisms, Capacity Estimation and Mitigations. | Dmitry Evtyushkin, Dmitry V. Ponomarev |
| 2016 | DAC | A high-resolution side-channel attack on last-level cache. | Mehmet Kayaalp, Nael B. Abu-Ghazaleh, Dmitry V. Ponomarev, Aamer Jaleel |
| 2016 | MICRO | Jump over ASLR: Attacking branch predictors to bypass ASLR. | Dmitry Evtyushkin, Dmitry V. Ponomarev, Nael B. Abu-Ghazaleh |
| 2015 | HPCA | Malware-aware processors: A framework for efficient online malware detection. | Meltem Ozsoy, Caleb Donovick, Iakov Gorelik, Nael B. Abu-Ghazaleh, Dmitry V. Ponomarev |
| 2015 | ISCA | Covert channels through branch predictors: a feasibility study. | Dmitry Evtyushkin, Dmitry V. Ponomarev, Nael B. Abu-Ghazaleh |
| 2015 | RAID | Ensemble Learning for Low-Level Hardware-Supported Malware Detection. | Khaled N. Khasawneh, Meltem Ozsoy, Caleb Donovick, Nael B. Abu-Ghazaleh, Dmitry V. Ponomarev |
| 2014 | ICCD | Dynamic associative caches: Reducing dynamic energy of first level caches. | Karthikeyan Dayalan, Meltem Ozsoy, Dmitry V. Ponomarev |
| 2014 | MICRO | Iso-X: A Flexible Architecture for Hardware-Managed Isolated Execution. | Dmitry Evtyushkin, Jesse Elwell, Meltem Ozsoy, Dmitry V. Ponomarev, Nael B. Abu-Ghazaleh, Ryan Riley |
| 2014 | PADS | Exploring many-core architecture design space for parallel discrete event simulation. | Yi Zhang, Jingjing Wang, Dmitry V. Ponomarev, Nael B. Abu-Ghazaleh |
| 2012 | PADS | Partitioning on Dynamic Behavior for Parallel Discrete Event Simulation. | Ketan Bahulkar, Jingjing Wang, Nael B. Abu-Ghazaleh, Dmitry V. Ponomarev |
| 2012 | PADS | Characterizing and Understanding PDES Behavior on Tilera Architecture. | Deepak Jagtap, Ketan Bahulkar, Dmitry V. Ponomarev, Nael B. Abu-Ghazaleh |
| 2012 | PADS | Performance Analysis of a Multithreaded PDES Simulator on Multicore Clusters. | Jingjing Wang, Dmitry V. Ponomarev, Nael B. Abu-Ghazaleh |
| 2009 | DAC | MPTLsim: a simulator for X86 multicore processors. | Hui Zeng, Matt T. Yourst, Kanad Ghose, Dmitry V. Ponomarev |
| 2008 | SBAC-PAD | Hiding Communication Delays in Clustered Microarchitectures. | Robert J. LaDuca, Joseph J. Sharkey, Dmitry V. Ponomarev |
| 2008 | SBAC-PAD | Accurate and Low-Overhead Dynamic Detection and Prediction of Program Phases Using Branch Signatures. | Balaji Vijayn, Dmitry V. Ponomarev |
| 2007 | ICS | An L2-miss-driven early register deallocation for SMT processors. | Joseph J. Sharkey, Dmitry V. Ponomarev |
| 2006 | HiPC | Trade-Offs in Transient Fault Recovery Schemes for Redundant Multithreaded Processors. | Joseph J. Sharkey, Nayef Abu-Ghazeleh, Dmitry V. Ponomarev, Kanad Ghose, Aneesh Aggarwal |
| 2006 | HPCA | Efficient instruction schedulers for SMT processors. | Joseph J. Sharkey, Dmitry V. Ponomarev |
| 2005 | EuroPar | Non-uniform Instruction Scheduling. | Joseph J. Sharkey, Dmitry V. Ponomarev |
| 2005 | EuroPar | Instruction Recirculation: Eliminating Counting Logic in Wakeup-Free Schedulers. | Joseph J. Sharkey, Dmitry V. Ponomarev |
| 2005 | ICCD | Power-Efficient Wakeup Tag Broadcast. | Joseph J. Sharkey, Kanad Ghose, Dmitry V. Ponomarev, Oguz Ergin |
| 2005 | ISLPED | Instruction packing: reducing power and delay of the dynamic scheduling logic. | Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose, Oguz Ergin |
| 2004 | ICCD | Increasing Processor Performance Through Early Register Release. | Oguz Ergin, Deniz Balkan, Dmitry V. Ponomarev, Kanad Ghose |
| 2004 | MICRO | Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure. | Oguz Ergin, Deniz Balkan, Kanad Ghose, Dmitry V. Ponomarev |
| 1998 | HiPC | A comparative study of some network subsystem organizations. | Dmitry V. Ponomarev, Kanad Ghose |