| 2015 | DATE | De-elastisation: from asynchronous dataflows to synchronous circuits. | Mahdi Jelodari Mamaghani, Jim D. Garside, Doug A. Edwards |
| 2014 | DSD | Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA. | Mahdi Jelodari Mamaghani, Jim D. Garside, William B. Toms, Doug A. Edwards |
| 2014 | ISCAS | Automatic data path extraction in large-scale register-transfer level designs. | Wei Song, Jim D. Garside, Doug A. Edwards |
| 2012 | DATE | Area efficient asynchronous SDM routers using 2-stage Clos switches. | Wei Song, Doug A. Edwards, Jim D. Garside, William J. Bainbridge |
| 2010 | ASPDAC | A low latency wormhole router for asynchronous on-chip networks. | Wei Song, Doug A. Edwards |
| 2010 | DDECS | Computation reduction for statistical analysis of the effect of nano-CMOS variability on asynchronous circuits. | Zheng Xie, Doug A. Edwards |
| 2010 | DSD | Description-Level Optimisation of Synthesisable Asynchronous Circuits. | Luis A. Tarazona, Doug A. Edwards, Andrew Bardsley, Luis A. Plana |
| 2009 | DSD | A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor. | Luis A. Tarazona, Doug A. Edwards, Luis A. Plana |
| 2007 | CASES | Performance-driven syntax-directed synthesis of asynchronous processors. | Luis A. Plana, Doug A. Edwards, Sam Taylor, Luis A. Tarazona, Andrew Bardsley |
| 2005 | ICCD | Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance. | Luis A. Plana, Sam Taylor, Doug A. Edwards |
| 2005 | VLSID | Synthesis of Asynchronous Circuits Using Early Data Validity. | Nitin Gupta, Doug A. Edwards |
| 2002 | DATE | A Burst-Mode Oriented Back-End for the Balsa Synthesis System. | Tiberiu Chelcea, Steven M. Nowick, Andrew Bardsley, Doug A. Edwards |