E. George Walters III
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
3
Active years
2005–2015
Best venue rank
National
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2015 | ACSSC | 24-bit significand multiplier for FPGA floating-point multiplication. | E. George Walters III |
| 2014 | ACSSC | Partial-product generation and addition for multiplication in FPGAs with 6-input LUTs. | E. George Walters III |
| 2014 | ISCAS | Optimized cubic chebyshev interpolator for elementary function hardware implementations. | Masoud Sadeghian, James E. Stine, E. George Walters III |
| 2012 | ACSSC | FPGA-accelerated simulation of truncated-matrix multipliers. | E. George Walters III |
| 2011 | ACSSC | Truncated-matrix multipliers with coefficient shifting. | E. George Walters III, Michael J. Schulte |
| 2005 | ARITH | Efficient Function Approximation Using Truncated Multipliers and Squarers. | E. George Walters III, Michael J. Schulte |