| 2023 | DAC | Equality Saturation for Datapath Synthesis: A Pathway to Pareto Optimality. | Ecenur Ustun, Cunxi Yu, Zhiru Zhang |
| 2022 | FCCM | IMpress: Large Integer Multiplication Expression Rewriting for FPGA HLS. | Ecenur Ustun, Ismail San, Jiaqi Yin, Cunxi Yu, Zhiru Zhang |
| 2021 | FPGA | AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs. | Licheng Guo, Yuze Chi, Jie Wang, Jason Lau, Weikang Qiao, Ecenur Ustun, Zhiru Zhang, Jason Cong |
| 2021 | ICCAD | GraphLily: Accelerating Graph Linear Algebra on HBM-Equipped FPGAs. | Yuwei Hu, Yixiao Du, Ecenur Ustun, Zhiru Zhang |
| 2020 | ICCAD | Accurate Operation Delay Prediction for FPGA HLS Using Graph Neural Networks. | Ecenur Ustun, Chenhui Deng, Debjit Pal, Zhijing Li, Zhiru Zhang |
| 2019 | FCCM | LAMDA: Learning-Assisted Multi-stage Autotuning for FPGA Design Closure. | Ecenur Ustun, Shaojie Xiang, Jinny Gui, Cunxi Yu, Zhiru Zhang |
| 2018 | FCCM | Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning. | Steve Dai, Yuan Zhou, Hang Zhang, Ecenur Ustun, Evangeline F. Y. Young, Zhiru Zhang |
| 2018 | FPGA | DATuner: An Extensible Distributed Autotuning Framework for FPGA Design and Design Automation: (Abstract Only). | Gai Liu, Ecenur Ustun, Shaojie Xiang, Chang Xu, Guojie Luo, Zhiru Zhang |