| 2024 | SECRYPT | FPGA Implementation of AES-Based on Optimized Dynamic s-Box. | Calvo Mayaudn Haroldo, Nakojah Chris David, Mahdi Madani, El-Bay Bourennane |
| 2021 | DASC | Multi-Grid Redundant Bounding Box Annotation for Accurate Object Detection. | Solomon Negussie Tesema, El-Bay Bourennane |
| 2014 | CoDIT | Implementation of universal digital architecture using 3D-NoC for mobile terminal. | Atef Benhaoues, El-Bay Bourennane, Camel Tanougast, Hichem Mayache, Salah Toumi, Kamel Messaoudi |
| 2012 | RSP | Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT. | Gilberto Ochoa-Ruiz, Ouassila Labbani, El-Bay Bourennane, Sana Cherif, Samy Meftali, Jean-Luc Dekeyser |
| 2011 | FDL | IP-XACT and marte based approach for partially reconfigurable systems-on-chip. | Gilberto Ochoa, El-Bay Bourennane, Ouassila Labbani, Kamel Messaoudi |
| 2004 | ICIP | Implementation of JPEG2000 arithmetic decoder using dynamic reconfiguration of FPGA. | Sophie Bouchoux, El-Bay Bourennane, Michel Paindavoine |
| 2002 | ICASSP | Real-time flaw detection on complex part: Study of SVM and hyperrectangle based method. | Sebastien Bouillant, Johel Mitran, El-Bay Bourennane, Michel Paindavoine |
| 2002 | ICASSP | Cost comparison of image rotation implantations on static and dynamic Reconfigurable FPGAs. | El-Bay Bourennane, Sophie Bouchoux, Johel Mitran, Michel Paindavoine, Sebastien Bouillant |
| 1998 | ICIP | Implementation of a Real Time Image Rotation using B-Spline Interpolation on FPGA's Board. | Cyril Berthaud, El-Bay Bourennane, Michel Paindavoine, Claude Milan |