Skip to content

Eric Rotenberg

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

41

Venues

10

Active years

1996–2026

Best venue rank

A*

Where they publish

Papers

41 indexed papers, newest first.

YearVenueTitleAuthors
2026ISCAAugmenting the Branch Predictor with a Squashed-Branch Reuse Buffer.Rohit Singh, Jiayang Li, Eric Rotenberg
2025HPCASpecMPK: Efficient In-Process Isolation with Speculative and Secure Permission Update Instruction.Debpratim Adak, Huiyang Zhou, Eric Rotenberg, Amro Awad
2025HPCADelinquent Loop Pre-execution Using Predicated Helper Threads.Anirudh Seshadri, Eric Rotenberg
2025MICROCryptoBTB: A Secure Hierarchical BTB for Diverse Instruction Footprint Workloads.Debpratim Adak, Eric Rotenberg, Amro Awad, Huiyang Zhou
2021MICROPost-Fabrication Microarchitecture.Chanchal Kumar, Anirudh Seshadri, Aayush Chaudhary, Shubham Bhawalkar, Rohit Singh, Eric Rotenberg
2020ISCASlipstream Processors Revisited: Exploiting Branch Sets.Vinesh Srinivasan, Rangeen Basu Roy Chowdhury, Eric Rotenberg
2017ICCDH3 (Heterogeneity in 3D): A Logic-on-Logic 3D-Stacked Heterogeneous Multi-Core Processor.Vinesh Srinivasan, Rangeen Basu Roy Chowdhury, Elliott Forbes, Randy Widialaksono, Zhenqian Zhang, Joshua Schabel, Sungkwan Ku, Steve Lipa, Eric Rotenberg, W. Rhett Davis, Paul D. Franzon
2016ICCDFast register consolidation and migration for heterogeneous multi-core processors.Elliott Forbes, Eric Rotenberg
2016ISPASSAnyCore: A synthesizable RTL model for exploring and fabricating adaptive superscalar cores.Rangeen Basu Roy Chowdhury, Anil K. Kannepalli, Sungkwan Ku, Eric Rotenberg
2014ASPDACCo-simulation framework for streamlining microprocessor development on standard ASIC design flow.Tomoyuki Nakabayashi, Tomoyuki Sugiyama, Takahiro Sasaki, Eric Rotenberg, Toshio Kondo
2014ICCDDesign-effort alloy: Boosting a highly tuned primary core with untuned alternate cores.Elliott Forbes, Niket Kumar Choudhary, Brandon H. Dwiel, Eric Rotenberg
2013ICCDRationale for a 3D heterogeneous multi-core processor.Eric Rotenberg, Brandon H. Dwiel, Elliott Forbes, Zhenqian Zhang, Randy Widialaksono, Rangeen Basu Roy Chowdhury, Nyunyi M. Tshibangu, Steve Lipa, W. Rhett Davis, Paul D. Franzon
2012ISPASSFPGA modeling of diverse superscalar processors.Brandon H. Dwiel, Niket Kumar Choudhary, Eric Rotenberg
2012MICROControl-Flow Decoupling.Rami Sheikh, James Tuck, Eric Rotenberg
2011ISCAFabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template.Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay A. Shah, Hiran Mayukh, Jayneel Gandhi, Brandon H. Dwiel, Sandeep Navada, Hashem Hashemi Najaf-abadi, Eric Rotenberg
2009HPCAArchitectural Contesting.Hashem Hashemi Najaf-abadi, Eric Rotenberg
2008DSNCoverage of a microarchitecture-level fault check regimen in a superscalar processor.Vimal K. Reddy, Eric Rotenberg
2008ISPASSConfigurational Workload Characterization.Hashem Hashemi Najaf-abadi, Eric Rotenberg
2007DSNInherent Time Redundancy (ITR): Using Program Repetition for Low-Overhead Fault Tolerance.Vimal K. Reddy, Eric Rotenberg
2007ISCATransparent control independence (TCI).Ahmed S. Al-Zawawi, Vimal K. Reddy, Eric Rotenberg, Haitham Akkary
2006ASPLOSUnderstanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance.Vimal K. Reddy, Eric Rotenberg, Sailashri Parthasarathy
2006HPCARetention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM.Ravi K. Venkatesan, Stephen Herr, Eric Rotenberg
2006ICCDAssertion-Based Microarchitecture Design for Improved Reliability.Vimal K. Reddy, Eric Rotenberg, Ahmed S. Al-Zawawi
2005CASESVirtual multiprocessor: an analyzable, high-performance architecture for real-time computing.Ali El-Haj-Mahmoud, Ahmed S. Al-Zawawi, Aravindh Anantaraman, Eric Rotenberg
2005HPCATapping ZettaRAMRavi K. Venkatesan, Ahmed S. Al-Zawawi, Eric Rotenberg
2004CASESSafely exploiting multithreaded processors to tolerate memory latency in real-time systems.Ali El-Haj-Mahmoud, Eric Rotenberg
2004RTSSEnforcing Safety of Real-Time Schedules on Contemporary Processors Using a Virtual Simple Architecture (VISA).Aravindh Anantaraman, Kiran Seth, Eric Rotenberg, Frank Mueller
2003HPCASlipstream Execution Mode for CMP-Based Multiprocessors.Khaled Z. Ibrahim, Gregory T. Byrd, Eric Rotenberg
2003ISCAVirtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems.Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, Eric Rotenberg, Frank Mueller
2003RTSSFAST: Frequency-Aware Static Timing Analysis.Kiran Seth, Aravindh Anantaraman, Frank Mueller, Eric Rotenberg
2002CASESA case for dynamic pipeline scaling.Jinson Koppanalil, Prakash Ramrakhyani, Sameer Desai, Anu Vaidyanathan, Eric Rotenberg
2002ISCAA Large, Fast Instruction Window for Tolerating Cache Misses.Alvin R. Lebeck, Tong Li, Eric Rotenberg, Jinson Koppanalil, Jaidev P. Patwardhan
2001MICROUsing variable-MHz microprocessors to efficiently handle uncertainty in real-time systems.Eric Rotenberg
2000ASPLOSSlipstream Processors: Improving both Performance and Fault Tolerance.Karthik Sundaramoorthy, Zachary Purser, Eric Rotenberg
2000MICROA study of slipstream processors.Zachary Purser, Karthik Sundaramoorthy, Eric Rotenberg
1999HPCAA Study of Control Independence in Superscalar Processors.Eric Rotenberg, Quinn Jacobson, James E. Smith
1999MICROControl Independence in Trace Processors.Eric Rotenberg, James E. Smith
1997MICROPath-Based Next Trace Prediction.Quinn Jacobson, Eric Rotenberg, James E. Smith
1997MICROTrace Processors.Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, James E. Smith
1996MICROAssigning Confidence to Conditional Branch Predictions.Erik Jacobsen, Eric Rotenberg, James E. Smith
1996MICROTrace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching.Eric Rotenberg, Steve Bennett, James E. Smith