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Erik Wehr

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

3

Venues

1

Active years

2024–2026

Best venue rank

C

Where they publish

Papers

3 indexed papers, newest first.

YearVenueTitleAuthors
2026ISCASA 240-to-945MHz 8-Phase PLL Clock Synthesizer With 1.22° Skew Calibration in 180nm HV CMOS for Closed-Loop Digital SiC/GaN Gate Driving.Erik Wehr, Tobias Zekorn, Kenny Vohl, Ralf Wunderlich, Stefan Heinen
2024ISCASA Trimming-Less External-RC Relaxation Oscillator With Self-Calibrating Current Reference for a SiC Active Gate Driver Application.Erik Wehr, Tobias Zekorn, Michael Hanhart, Kenny Vohl, Lon Weihs, Ralf Wunderlich, Stefan Heinen
2024ISCASA High-Voltage Single-Inductor Multiple-Output DC-DC Buck Converter for the Power Management Unit of a Gate-Shaping Digital Gate Driver.Tobias Zekorn, Florian Schimkat, Kenny Vohl, Erik Wehr, Ralf Wunderlich, Stefan Heinen