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A 240-to-945MHz 8-Phase PLL Clock Synthesizer With 1.22° Skew Calibration in 180nm HV CMOS for Closed-Loop Digital SiC/GaN Gate Driving.

Erik Wehr, Tobias Zekorn, Kenny Vohl, Ralf Wunderlich, Stefan Heinen

VenueCISCAS
Year2026
ProceedingsISCAS

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