A 240-to-945MHz 8-Phase PLL Clock Synthesizer With 1.22° Skew Calibration in 180nm HV CMOS for Closed-Loop Digital SiC/GaN Gate Driving.
Erik Wehr, Tobias Zekorn, Kenny Vohl, Ralf Wunderlich, Stefan Heinen
Browse the full ISCAS paper archive.
Erik Wehr, Tobias Zekorn, Kenny Vohl, Ralf Wunderlich, Stefan Heinen
Browse the full ISCAS paper archive.