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Ernest S. Kuh

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

42

Venues

9

Active years

1979–2009

Best venue rank

A*

Where they publish

Papers

42 indexed papers, newest first.

YearVenueTitleAuthors
2009ASPDACHigh performance on-chip differential signaling using passive compensation for global communication.Ling Zhang, Yulei Zhang, Akira Tsuchiya, Masanori Hashimoto, Ernest S. Kuh, Chung-Kuan Cheng
2008DACLow power passive equalizer optimization using tritonic step response.Ling Zhang, Wenjian Yu, Haikun Zhu, Alina Deutsch, George A. Katopis, Daniel M. Dreps, Ernest S. Kuh, Chung-Kuan Cheng
2008HOTILow Power Passive Equalizer Design for Computer Memory Links.Ling Zhang, Wenjian Yu, Yulei Zhang, Renshen Wang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng
2008ICCADEfficient and accurate eye diagram prediction for high speed signaling.Rui Shi, Wenjian Yu, Yi Zhu, Chung-Kuan Cheng, Ernest S. Kuh
2006ASPDACAn unconditional stable general operator splitting method for transistor level transient analysis.Zhengyong Zhu, Rui Shi, Chung-Kuan Cheng, Ernest S. Kuh
2005ASPDACEfficient transient simulation for transistor-level analysis.Zhengyong Zhu, Khosro Rouz, Manjit Borah, Chung-Kuan Cheng, Ernest S. Kuh
2001DATEExplicit formulas and efficient algorithm for moment computation of coupled RC trees with lumped and distributed elements.Qingjian Yu, Ernest S. Kuh
2000DACFloorplan sizing by linear programming approximation.Pinghong Chen, Ernest S. Kuh
2000DACPassive model order reduction algorithm based on Chebyshev expansion of impulse response of interconnect networks.Qingjian Yu, Janet Meiling Wang, Ernest S. Kuh
1999DATECoupled Noise Estimation for Distributed RC Interconnect Model.Janet Meiling Wang, Qingjian Yu, Ernest S. Kuh
1999ICCADThe Chebyshev expansion based passive model for distributed interconnect networks.Janet Meiling Wang, Ernest S. Kuh, Qingjian Yu
1998DATEA Performance-Driven MCM Router with Special Consideration of Crosstalk Reduction.Dongsheng Wang, Ernest S. Kuh
1998ICCADMultipoint moment matching model for multiport distributed interconnect networks.Qingjian Yu, Janet Meiling Wang, Ernest S. Kuh
1997VLSIDSYMPHONY: A Fast Mixed Signal Simulator for BiMOS Analog/Digital Circuits.Premal Buch, Ernest S. Kuh
1996ICCADSimulation and sensitivity analysis of transmission line circuits by the characteristics method.Jun-Fa Mao, Janet Meiling Wang, Ernest S. Kuh
1996ICCADPost global routing crosstalk risk estimation and reduction.Tianxiong Xue, Ernest S. Kuh, Dongsheng Wang
1995ICCADPost routing performance optimization via multi-link insertion and non-uniform wiresizing.Tianxiong Xue, Ernest S. Kuh
1995ISLPEDTechniques for fast circuit simulation applied to power estimation of CMOS circuits.Premal Buch, Shen Lin, Vijay Nagasamy, Ernest S. Kuh
1993DACPerformance-Driven Steiner Tree Algorithm for Global Routing.Xianlong Hong, Tianxiong Xue, Ernest S. Kuh, Chung-Kuan Cheng, Jin Huang
1993DACAn Efficient Timing-Driven Global Routing Algorithm.Jin Huang, Xianlong Hong, Chung-Kuan Cheng, Ernest S. Kuh
1993DACQuadratic Boolean Programming for Performance-Driven System Partitioning.Minshine Shih, Ernest S. Kuh
1993ICCADA spacing algorithm for performance enhancement and cross-talk reduction.Kamal Chaudhary, Akira Onozawa, Ernest S. Kuh
1992DACFARM: An Efficient Feed-Through Pin Assignment Algorithm.Xianlong Hong, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh
1992DACTransient Simulation of Lossy Interconnect.Shen Lin, Ernest S. Kuh
1992DACPower and Ground Network Topology Optimization for Cell Based VLSIs.Takashi Mitsuhashi, Ernest S. Kuh
1992DACPerformance-Driven System Partitioning on Multi-Chip Modules.Minshine Shih, Ernest S. Kuh, Ren-Song Tsay
1992VLSIDA New Accurate and Efficient Timing Simulator.Shen Lin, Ernest S. Kuh, Malgorzata Marek-Sadowska
1991ICCADRITUAL: Performance Driven Placement Algorithm for Small Cell ICs.Arvind Srinivasan, Kamal Chaudhary, Ernest S. Kuh
1991ICCDI/O Pad Assignment Based on the Circuit Structure.Massoud Pedram, Kamal Chaudhary, Ernest S. Kuh
1990DACClock Routing for High-Performance ICs.Michael A. B. Jackson, Arvind Srinivasan, Ernest S. Kuh
1990DACDelay and Area Optimization in Standard-Cell Design.Shen Lin, Malgorzata Marek-Sadowska, Ernest S. Kuh
1990ICCADA Fast Algorithm for Performance-Driven Placement.Michael A. B. Jackson, Arvind Srinivasan, Ernest S. Kuh
1990ICCADFloorplanning with Pin Assignment.Massoud Pedram, Malgorzata Marek-Sadowska, Ernest S. Kuh
1989DACPerformance-driven Placement of Cell Based IC's.Michael A. B. Jackson, Ernest S. Kuh
1988DACProud: A Fast Sea-of-Gates Placement Algorithm.Ren-Song Tsay, Ernest S. Kuh, Chi-Ping Hsu
1988DACThe Constrained Via Minimization Problem for PCB and VLSI Design.Xiao-Ming Xiong, Ernest S. Kuh
1988ICCADHierarchical placement for macrocells: a 'meet in the middle' approach.Bernhard Eschermann, Wayne Wei-Ming Dai, Ernest S. Kuh, Massoud Pedram
1987DACA Dynamic and Efficient Representation of Building-Block Layout.Wayne Wei-Ming Dai, Masao Sato, Ernest S. Kuh
1987DACNutcracker: An Efficient and Intelligent Channel Spacer.Xiao-Ming Xiong, Ernest S. Kuh
1981DACOn the layering problem of multilayer PWB wiring.Shuji Tsukiyama, Ernest S. Kuh, Isao Shirakawa
1979COMPSACSingle-row routing and extensions.Ernest S. Kuh
1979COMPSACOne-dimensional logic gate assignment and interval graphs.Tatsuo Ohtsuki, Hajimu Mori, Ernest S. Kuh, Toshinobu Kashiwabara, Toshio Fujisawa