Esdras Jurez-Hernndez
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
2003–2020
Best venue rank
A
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2020 | ITC | High Speed Serial Links Risk Assessment in Industrial Post-Silicon Validation Exploiting Machine Learning Techniques. | Cesar A. Snchez-Martnez, Paulo Lpez-Meyer, Esdras Jurez-Hernndez, Aaron Desiga-Orenday, Andrs Viveros-Wacher |
| 2003 | ISCAS | A 1.35 GHz CMOS wideband frequency synthesizer for mobile communications. | Esdras Jurez-Hernndez, Alejandro Daz-Snchez, Esteban Tlelo-Cuautle |