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Federico Angiolini

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

19

Venues

7

Active years

2003–2017

Best venue rank

A*

Where they publish

Papers

19 indexed papers, newest first.

YearVenueTitleAuthors
2017DATE1024-Channel 3D ultrasound digital beamformer in a single 5W FPGA.Federico Angiolini, Aya Ibrahim, William Andrew Simon, Ahmet Caner Yuzuguler, Marcel Arditi, Jean-Philippe Thiran, Giovanni De Micheli
2016FPLSingle-FPGA, scalable, low-power, and high-quality 3D ultrasound beamformer.William Andrew Simon, Ahmet Caner Yuzuguler, Aya Ibrahim, Federico Angiolini, Marcel Arditi, Jean-Philippe Thiran, Giovanni De Micheli
2016FPLSingle-FPGA 3D ultrasound beamformer.Ahmet Caner Yuzuguler, William Andrew Simon, Aya Ibrahim, Federico Angiolini, Marcel Arditi, Jean-Philippe Thiran, Giovanni De Micheli
2015DATETackling the bottleneck of delay tables in 3D ultrasound imaging.Aya Ibrahim, Pascal Hager, Andrea Bartolini, Federico Angiolini, Marcel Arditi, Luca Benini, Giovanni De Micheli
2014ASPDACA vertically integrated and interoperable multi-vendor synthesis flow for predictable noc design in nanoscale technologies.Alberto Ghiribaldi, Herv Tatenguem Fankem, Federico Angiolini, Mikkel Bystrup Stensgaard, Tobias Bjerregaard, Davide Bertozzi
2010DACNetworks on Chips: from research to products.Giovanni De Micheli, Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Federico Angiolini, Antonio Pullini
2009DATESynthesis of low-overhead configurable source routing tables for network interfaces.Igor Loi, Federico Angiolini, Luca Benini
2009ICCADA method for calculating hard QoS guarantees for Networks-on-Chip.Dara Rahmati, Srinivasan Murali, Luca Benini, Federico Angiolini, Giovanni De Micheli, Hamid Sarbazi-Azad
2008DATEDeveloping Mesochronous Synchronizers to Enable 3D NoCs.Igor Loi, Federico Angiolini, Luca Benini
2007DATEInteractive presentation: Improving the fault tolerance of nanometric PLA designs.Federico Angiolini, M. Haykel Ben Jamaa, David Atienza, Luca Benini, Giovanni De Micheli
2006DATEAn integrated open framework for heterogeneous MPSoC design space exploration.Federico Angiolini, Jianjiang Ceng, Rainer Leupers, Federico Ferrari, Cesare Ferri, Luca Benini
2006DATEContrasting a NoC and a traditional interconnect fabric with layout awareness.Federico Angiolini, Paolo Meloni, Salvatore Carta, Luca Benini, Luigi Raffo
2006ICCADDesigning application-specific networks on chips with floorplan information.Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
2006ICCDReliability Support for On-Chip Memories Using Networks-on-Chip.Federico Angiolini, David Atienza, Srinivasan Murali, Luca Benini, Giovanni De Micheli
2005DATEA Network Traffic Generator Model for Fast Network-on-Chip Simulation.Shankar Mahadevan, Federico Angiolini, Michael Storgaard, Rasmus Grndahl Olsen, Jens Spars, Jan Madsen
2005DATExpipes Lite: A Synthesis Oriented Design Library For Networks on Chips.Stergios Stergiou, Federico Angiolini, Salvatore Carta, Luigi Raffo, Davide Bertozzi, Giovanni De Micheli
2004CASESA post-compiler approach to scratchpad mapping of code.Federico Angiolini, Francesco Menichelli, Alberto Ferrero, Luca Benini, Mauro Olivieri
2004DATEAnalyzing On-Chip Communication in a MPSoC Environment.Mirko Loghi, Federico Angiolini, Davide Bertozzi, Luca Benini, Roberto Zafalon
2003CASESPolynomial-time algorithm for on-chip scratchpad memory partitioning.Federico Angiolini, Luca Benini, Alberto Caprara