| 2009 | ASPDAC | Partial order method for timed simulation of system-level MPSoC designs. | Eric Cheung, Harry Hsieh, Felice Balarin |
| 2009 | ASPDAC | Fast and accurate performance simulation of embedded software for MPSoC. | Eric Cheung, Harry Hsieh, Felice Balarin |
| 2009 | ASPDAC | Memory subsystem simulation in software TLM/T models. | Eric Cheung, Harry Hsieh, Felice Balarin |
| 2006 | DATE | Functional verification methodology based on formal interface specification and transactor generation. | Felice Balarin, Roberto Passerone |
| 2006 | DATE | Communication and co-simulation infrastructure for heterogeneous system integration. | Guang Yang, Xi Chen, Felice Balarin, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli |
| 2005 | DATE | Assertion-Based Design Exploration of DVS in Network Processor Architectures. | Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin |
| 2005 | MEMOCODE | A formal approach to system level design: metamodels and unified design environments. | Felice Balarin, Roberto Passerone, Alessandro Pinto, Alberto L. Sangiovanni-Vincentelli |
| 2004 | DATE | Utilizing Formal Assertions for System Design of Network Processors. | Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Felice Balarin |
| 2004 | EMSOFT | Separation of concerns: overhead in modeling and efficient simulation techniques. | Guang Yang, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe, Felice Balarin |
| 2003 | DAC | Automatic trace analysis for logic of constraints. | Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe |
| 2003 | DATE | Automatic Generation of Simulation Monitors from Quantitative Constraint Formula. | Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe |
| 2002 | EMSOFT | Processes, Interfaces and Platforms. Embedded Software Modeling in Metropolis. | Felice Balarin, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe |
| 2001 | ICCAD | Stars in VCC: Complementing Simulation with Worst-Case Analysis. | Felice Balarin |
| 2001 | RTAS | Scheduling Reactive Task Graphs in Embedded Control Systems. | Marco Di Natale, Alberto L. Sangiovanni-Vincentelli, Felice Balarin |
| 2000 | DAC | Efficient methods for embedded system design space exploration. | Harry Hsieh, Felice Balarin, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli |
| 2000 | DAC | Task scheduling with RT constraints. | Marco Di Natale, Alberto L. Sangiovanni-Vincentelli, Felice Balarin |
| 2000 | DATE | Automatic Abstraction for Worst-Case Analysis of Discrete Systems. | Felice Balarin |
| 1999 | ICCAD | Worst-case analysis of discrete systems. | Felice Balarin |
| 1999 | ICCAD | Synchronous equivalence for embedded systems: a tool for design exploration. | Harry Hsieh, Felice Balarin |
| 1999 | ICCD | Software Synthesis for Complex Reactive Embedded Systems. | Felice Balarin, Massimiliano Chiodo |
| 1998 | CAV | Correctness of the Concurrent Approach to Symbolic Verification of Interleaved Models. | Felice Balarin |
| 1997 | DAC | Schedule Validation for Embedded Reactive Real-Time Systems. | Felice Balarin, Alberto L. Sangiovanni-Vincentelli |
| 1996 | DAC | Formal Verification of Embedded Systems based on CFSM Networks. | Felice Balarin, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli |
| 1996 | RTSS | Approximate reachability analysis of timed automata. | Felice Balarin |
| 1995 | CAV | Supervisory Control of Finite State Machines. | Adnan Aziz, Felice Balarin, Robert K. Brayton, Marika Domenica Di Benedetto, Alexander Saldanha |
| 1995 | CAV | It Usually Works: The Temporal Logic of Stochastic Systems. | Adnan Aziz, Vigyan Singhal, Felice Balarin |
| 1995 | ICCAD | Sequential synthesis using S1S. | Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1994 | CAV | On the Automatic Computation of Network Invariants. | Felice Balarin, Alberto L. Sangiovanni-Vincentelli |
| 1994 | DAC | HSIS: A BDD-Based Environment for Formal Verification. | Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1994 | ICALP | Equivalences for Fair Kripke Structures. | Adnan Aziz, Vigyan Singhal, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1994 | ICCAD | Iterative algorithms for formal verification of embedded real-time systems. | Felice Balarin, Alberto L. Sangiovanni-Vincentelli |
| 1993 | CAV | An Iterative Approach to Language Containment. | Felice Balarin, Alberto L. Sangiovanni-Vincentelli |
| 1992 | CAV | A Verification Strategy for Timing-Constrained Systems. | Felice Balarin, Alberto L. Sangiovanni-Vincentelli |