Felipe S. Marranghello
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
9
Venues
4
Active years
2011–2021
Best venue rank
A*
Where they publish
Papers
9 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2021 | DAC | LUT-Based Optimization For ASIC Design Flow. | Luca Gaetano Amar, Vinicius N. Possani, Eleonora Testa, Felipe S. Marranghello, Christopher Casares, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli |
| 2020 | DAC | SAT-Sweeping Enhanced for Logic Synthesis. | Luca G. Amar, Felipe S. Marranghello, Eleonora Testa, Christopher Casares, Vinicius N. Possani, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli |
| 2015 | DSD | Enhanced Spin-Diode Synthesis Using Logic Sharing. | Mayler G. A. Martins, Felipe S. Marranghello, Joseph S. Friedman, Alan V. Sahakian, Renato P. Ribas, Andr Incio Reis |
| 2015 | ICCD | Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis. | Vinicius Callegaro, Felipe S. Marranghello, Mayler G. A. Martins, Renato P. Ribas, Andr Incio Reis |
| 2015 | ICCD | SOP based logic synthesis for memristive IMPLY stateful logic. | Felipe S. Marranghello, Vinicius Callegaro, Andr Incio Reis, Renato P. Ribas |
| 2015 | ISCAS | Improved logic synthesis for memristive stateful logic using multi-memristor implication. | Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, Andr Incio Reis, Renato P. Ribas |
| 2015 | ISCAS | Fast buffer delay estimation considering time-dependent dielectric breakdown. | Felipe S. Marranghello, Andr Incio Reis, Renato P. Ribas |
| 2014 | ISCAS | CMOS inverter analytical delay model considering all operating regions. | Felipe S. Marranghello, Andr Incio Reis, Renato P. Ribas |
| 2011 | ICCD | Impact and optimization of lithography-aware regular layout in digital circuit design. | Vincius Dal Bem, Paulo F. Butzen, Felipe S. Marranghello, Andr Incio Reis, Renato P. Ribas |