Francisco-Javier Veredas
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
4
Active years
2005–2018
Best venue rank
B
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2018 | DSD | FPGA Placement Improvement Using a Genetic Algorithm and the Routing Algorithm as a Cost Function. | Francisco-Javier Veredas, Enrique J. Carmona |
| 2006 | DATE | Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time. | Francisco-Javier Veredas, Michael Scheppler, Hans-Jrg Pfleiderer |
| 2006 | FPL | Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs. | Francisco-Javier Veredas, Hans-Jrg Pfleiderer |
| 2006 | ISCAS | LUT-based MPGAs for fast turnaround time conversion flow. | Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jrg Pfleiderer |
| 2005 | FPL | Mapping an H.264/AVC Decoder onto the ADRES Reconfigurable Architecture. | Bingfeng Mei, Francisco-Javier Veredas, Bart Masschelein |
| 2005 | FPL | Custom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia Purposes. | Francisco-Javier Veredas, Michael Scheppler, Will Moffat, Bingfeng Mei |