| 2026 | ISCAS | Fast and Accurate SystemVerilog Framework for Mixed-Signal Modeling of PAM-4 Wireline Transceivers. | Yujin Choi, Seongjin Kim, Seoyoung Jang, Donggeon Kim, Korkut Kaan Tokgoz, Gain Kim |
| 2026 | ISCAS | Fixed-Point Implementation Analysis of MLSE Receiver DSP for High-Speed Wireline Transceivers. | Dohyeon Kwon, Donggeon Kim, Yujin Choi, Yusuf Leblebici, Gain Kim |
| 2025 | ISLPED | A Spectral-Efficient Low-Power NRZ/PAM-4 Dual-Mode Wireline Transmitter for Multidrop Interfaces. | Donggeon Kim, Kiarash Gharibdoust, Armin Tajalli, Kyungtae Lee, Gain Kim |
| 2024 | ISCAS | DMT 3L4W: A 3-Lane 4-Wire Signaling With Discrete Multitone Modulation for High-Speed Wireline Chip-to-Chip Interconnects. | Seoyoung Jang, Jaewon Lee, Yujin Choi, Donggeon Kim, Gain Kim |
| 2024 | ISCAS | A 44 MIMO Discrete Multitone Wireline Transceiver With Far-End Crosstalk Cancellation For ADC-Based High-Speed Serial Links. | Jaewon Lee, Seoyoung Jang, Yujin Choi, Donggeon Kim, Matthias Braendli, Marcel A. Kossel, Andrea Ruffino, Thomas Morf, Pier Andrea Francese, Gain Kim |
| 2021 | ISCAS | Link Bit-Error-Rate Requirement Analysis for Deep Neural Network Accelerators. | Jaewon Lee, Gain Kim, Jinho Park, Hyeon-Min Bae |
| 2018 | ISCAS | Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver. | Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter zkaya, Thomas Toifl, Yusuf Leblebici |
| 2016 | ISCAS | A fully-digital spectrum shaping signaling for serial-data transceiver with crosstalk and ISI reduction property in multi-drop memory interfaces. | Kiarash Gharibdoust, Gain Kim, Armin Tajalli, Yusuf Leblebici |
| 2015 | FPGA | Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only). | Pierre-Emmanuel Gaillardon, Gain Kim, Xifan Tang, Luca Gaetano Amar, Giovanni De Micheli |