Gopal Vija
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
1998–1998
Best venue rank
A
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1998 | DATE | CMOS Combinational Circuit Sizing by Stage-wise Tapering. | Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija |