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H. Narayanan

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

20

Venues

6

Active years

1992–2016

Best venue rank

A*

Where they publish

Papers

20 indexed papers, newest first.

YearVenueTitleAuthors
2016VLSIDRelaxation Based Circuit Simulation Acceleration over CPU-FPGA.Vinay B. Y. Kumar, Kulshreshth Dhiman, Mandar Datar, Akash Pacharne, H. Narayanan, Sachin B. Patkar
2013VLSIDMemory Efficient Implementation of Two Graph Based Circuit Simulator for PDE-Electrical Analogy.Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar
2012VLSIDTwo Graph Based Circuit Simulator for PDE-Electrical Analogy.Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar
2009VLSIDFPGA Based High Performance Double-Precision Matrix Multiplication.Vinay B. Y. Kumar, Siddharth Joshi, Sachin B. Patkar, H. Narayanan
2009VLSIDExploiting Hybrid Analysis in Solving Electrical Networks.V. Siva Sankar, H. Narayanan, Sachin B. Patkar
2007ISCASApplication of Fast DC Analysis to Partitioning Hypergraphs.Gaurav Trivedi, H. Narayanan
2007VLSIDParallelization of DC Analysis through Multiport Decomposition.Gaurav Trivedi, Madhav P. Desai, H. Narayanan
2007VLSIDApplication of DC Analyzer to Combinatorial Optimization Problems.Gaurav Trivedi, Sumit Punglia, H. Narayanan
2006VLSIDFast DC Analysis and Its Application to Combinatorial Optimization Problems.Gaurav Trivedi, Madhav P. Desai, H. Narayanan
2003VLSIDAn Efficient Practical Heuristic For Good Ratio-Cut Partitioning.Sachin B. Patkar, H. Narayanan
2002VLSIDMathematical Methods in VLSI (Tutorial Abstract).M. V. Atre, P. S. Subramanian, H. Narayanan
2001VLSIDSpectral Algorithm To Compute And Synthesize Reduced Order Passive Models For Arbitrary Rc Multiports.Shabbir H. Batterywala, H. Narayanan
1999ICCDDecomposition of Finite State Machines for Area, Delay Minimization.Rupesh S. Shelar, Madhav P. Desai, H. Narayanan
1999VLSIDEfficient DC Analysis of RVJ Circuits for Moment and Derivative Commutations of Interconnect Networks.Shabbir H. Batterywala, H. Narayanan
1999VLSIDA State Assignment Scheme Targeting Performance and Area.B. N. V. Malleswara Gupta, H. Narayanan, Madhav P. Desai
1997VLSIDA New Partitioning Strategy Based on Supermodular Functions.Sachin B. Patkar, Shabbir H. Batterywala, M. Chandramouli, H. Narayanan
1994MFCSApproximation Algorithms for Min-k-overlap Problems Using the Principal Lattice of Partitions Approach.H. Narayanan, Subir K. Roy, Sachin B. Patkar
1993ISCASApplication of the principal partition and principal lattice of partitions of a graph to the problem of decomposition of a finite state machine.Subir K. Roy, H. Narayanan
1992ISAACPrincipal Lattice of Partition of submodular functions on Graphs: Fast algorithms for Principal Partition and Generic Rigidity.Sachin B. Patkar, H. Narayanan
1992SODARandomized Parallel Algorithms for Matroid Union and Intersection, with Applications to Arboresences and Edge-Disjoint Spanning Trees.H. Narayanan, Huzur Saran, Vijay V. Vazirani