Hamid Reza Pourshaghaghi
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
2
Active years
2011–2019
Best venue rank
C
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2019 | DSD | Fault Tolerant FPGAs: Where to Spend the Effort? | Mahsa Mousavi, Sayandip De, Hamid Reza Pourshaghaghi, Henk Corporaal |
| 2018 | DSD | A Generic Methodology to Compute Design Sensitivity to SEU in SRAM-Based FPGA. | Mahsa Mousavi, Hamid Reza Pourshaghaghi, Mohammad Tahghighi, Roel Jordans, Henk Corporaal |
| 2017 | DSD | Necessity of Fault Tolerance Techniques in Xilinx Kintex 7 FPGA Devices for Space Missions: A Case Study. | Louis D. van Harten, Roel Jordans, Hamid Reza Pourshaghaghi |
| 2012 | DATE | Sliding-Mode Control to Compensate PVT Variations in dual core systems. | Hamid Reza Pourshaghaghi, Hamed Fatemi, Jos Pineda de Gyvez |
| 2011 | DSD | Process Variation Reduction for CMOS Logic Operating at Sub-threshold Supply Voltage. | Bo Liu, Hamid Reza Pourshaghaghi, Sebastian M. Londono, Jos Pineda de Gyvez |