| 2009 | FPL | Numerically controlled oscillators using linear approximation. | Hans-Jrg Pfleiderer, Stefan Lachowicz |
| 2008 | FPL | FPGA implementation of a flexible decoder for long LDPC codes. | Christiane Beuschel, Hans-Jrg Pfleiderer |
| 2008 | FPL | EMMA - A suggestion for an embedded multi-precision multiplier array for FPGAs. | Oliver A. Pfnder, Hans-Jrg Pfleiderer |
| 2007 | ISCAS | Area and Throughput Aware Comparator Networks Optimization for Parallel Data Processing on FPGA. | Christophe Layer, Daniel Schaupp, Hans-Jrg Pfleiderer |
| 2006 | DATE | Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time. | Francisco-Javier Veredas, Michael Scheppler, Hans-Jrg Pfleiderer |
| 2006 | FPL | Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs. | Francisco-Javier Veredas, Hans-Jrg Pfleiderer |
| 2006 | ISCAS | LUT-based MPGAs for fast turnaround time conversion flow. | Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jrg Pfleiderer |
| 2004 | FPL | A Reconfigurable Recurrent Bitonic Sorting Network for Concurrently Accessible Data. | Christophe Layer, Hans-Jrg Pfleiderer |
| 2004 | FPL | A Multiplexer-Based Concept for Reconfigurable Multiplier Arrays. | Oliver A. Pfnder, Roland Hacker, Hans-Jrg Pfleiderer |
| 2004 | ISCAS | A scalable compact architecture for the computation of integer binary logarithms through linear approximation. | Christophe Layer, Hans-Jrg Pfleiderer, Christoph Heer |
| 2002 | FPL | Hardware Implementation of a Multiuser Detection Scheme Based on Recurrent Neural Networks. | Wolfgang Schlecker, Achim Engelhart, Werner G. Teich, Hans-Jrg Pfleiderer |
| 1994 | ISCAS | Large Bandwidth BiCMOS Operational Amplifiers for SC-Video-Applications. | Gerhard Nebel, Ulrich Kleine, Hans-Jrg Pfleiderer |