Haolin Ge
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2026–2026
Best venue rank
A
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | DATE | An Operator-Circuit Co-design Digital SOT-MRAM Computing-in-Memory Accelerator with Double Bit Density and Full-Utilized Bandwidth/Throughput. | Tianshuo Bai, Jingcheng Gu, Lehao Tan, Wente Yi, Haolin Ge, Han Zhang, Zhenyu Xue, He Zhang, Na Lei, Biao Pan |