Hari Ananthan
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
4
Active years
2004–2006
Best venue rank
A*
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2006 | DAC | A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS. | Hari Ananthan, Kaushik Roy |
| 2006 | VLSID | Double-Gate SOI Devices for Low-Power and High-Performance Applications. | Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici |
| 2005 | ICCAD | Double-gate SOI devices for low-power and high-performance applications. | Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici |
| 2004 | ISLPED | Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS. | Hari Ananthan, Chris H. Kim, Kaushik Roy |