Harsha Sathyamurthy
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
1995–1995
Best venue rank
A
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1995 | ICCAD | Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. | Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn |