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Hemangee K. Kapoor

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

36

Venues

11

Active years

2004–2025

Best venue rank

A*

Where they publish

Papers

36 indexed papers, newest first.

YearVenueTitleAuthors
2025VLSIDOptimizing Bandwidth Utilization Through Word Based Compression in Main Memories.N. S. Aswathy, Harsh Verma, Hemangee K. Kapoor
2025VLSIDABMF: Adaptive Bonsai Merkle Forests for Efficient Integrity Verification in Secure Persistent Memories.Hemangee K. Kapoor, Kartikay Bhardwaj
2025VLSIDE-DOSA: Efficient Dataflow for Optimising SNN Acceleration.Hemangee K. Kapoor, Imlijungla Longchar, Binayak Behera
2025VLSIDPAF-Enc: Position Affine Encoding to Reduce Bit-Flips in Non-Volatile Main Memories.Swati Upadhyay, Hemangee K. Kapoor
2024ICCDOpportunistic Migration for Hybrid Memories While Mitigating Aging Effects.N. S. Aswathy, Hemangee K. Kapoor
2024VLSIDBit-Beading: Stringing bit-level MAC results for Accelerating Neural Networks.Zeeshan Anwar, Imlijungla Longchar, Hemangee K. Kapoor
2023CCGRIDCCGRID 2023: A Holistic Approach to Inclusion and Belonging.Beth Plale, Preeti Malakar, Meenakshi D'Souza, Hemangee K. Kapoor, Yogesh Simmhan, Ilkay Altintas, Manohar Swaminathan
2023VLSIDWIB-SAR: Write Intensity Based Selective Address Remapping.N. S. Aswathy, Deep Bhuinya, Hemangee K. Kapoor
2022DATEHydra: A near hybrid memory accelerator for CNN inference.Palash Das, Ajay Joshi, Hemangee K. Kapoor
2022ISLPEDExploiting successive identical words and differences with dynamic bases for effective compression in Non-Volatile Memories.Swati Upadhyay, Arijit Nath, Hemangee K. Kapoor
2021RTCSAA Soft Real-time Memory Request Scheduler for Phase Change Memory Systems.N. S. Aswathy, Hemangee K. Kapoor, Arnab Sarkar
2020DACZENCO: Zero-bytes based ENCOding for Non-Volatile Buffers in On-Chip Interconnects.Khushboo Rani, Hemangee K. Kapoor
2020ISLPEDWELCOMF: wear leveling assisted compression using frequent words in non-volatile main memories.Arijit Nath, Hemangee K. Kapoor
2020ISLPEDDidaSel: dirty data based selection of VC for effective utilization of NVM buffers in on-chip interconnects.Khushboo Rani, Sukarn Agarwal, Hemangee K. Kapoor
2019DACImproving Static Power Efficiency via Placement of Network Demultiplexer over Control Plane of Router in Multi-NoCs.Sonal Yadav, Vijay Laxmi, Manoj Singh Gaur, Hemangee K. Kapoor
2019SACRefresh optimised embedded-dram caches based on zero data detection.Sheel Sindhu Manohar, Hemangee K. Kapoor
2019VLSIDWrite Variation Aware Cache Partitioning for Improved Lifetime in Non-volatile Caches.Arijit Nath, Hemangee K. Kapoor
2019VLSIDWrite Variation Aware Non-volatile Buffers for On-Chip Interconnects.Khushboo Rani, Hemangee K. Kapoor
2018VLSIDTowards Near Data Processing of Convolutional Neural Networks.Palash Das, Shivam Lakhotia, Prabodh Shetty, Hemangee K. Kapoor
2018VLSIDDPFair Scheduling with Slowdown and Suspension.Sanjay Moulik, Arnab Sarkar, Hemangee K. Kapoor
2018VLSIDFault Tolerance in Network on Chip Using Bypass Path Establishing Packets.Sharma Priya, Sukarn Agarwal, Hemangee K. Kapoor
2018VLSIDDynamic Thermal Management by Using Task Migration in Conjunction with Frequency Scaling for Chip Multiprocessors.Alankar V. Umdekar, Arijit Nath, Shirshendu Das, Hemangee K. Kapoor
2017VLSIDTowards a Better Lifetime for Non-volatile Caches in Chip Multiprocessors.Sukarn Agarwal, Hemangee K. Kapoor
2017VLSIDTowards Controlling Chip Temperature by Dynamic Cache Reconfiguration in Multiprocessors.Shounak Chakraborty, Hemangee K. Kapoor
2016SACStatic energy efficient cache reconfiguration for dynamic NUCA in tiled CMPs.Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor
2016SACDynamic associativity enabled DNUCA to improve block localisation in tiled CMPs.Shirshendu Das, Hemangee K. Kapoor
2016VLSIDTowards a Better Cache Utilization by Selective Data Storage for CMP Last Level Caches.Shirshendu Das, Hemangee K. Kapoor
2015SACDynamic associativity management using utility based way-sharing.Shirshendu Das, Hemangee K. Kapoor
2015SACStatic energy reduction by performance linked cache capacity management in tiled CMPs.Hemangee K. Kapoor, Shirshendu Das, Shounak Chakraborty
2015VLSIDExploration of Migration and Replacement Policies for Dynamic NUCA over Tiled CMPs.Shirshendu Das, Hemangee K. Kapoor
2014CITRT-DVS for Power Optimization in Multiprocessor Real-Time Systems.B. Venkateswarlu Naik, Shirshendu Das, Hemangee K. Kapoor
2014CITAn Approach for Multicast Routing in Networks-on-Chip.M. Lakshmi Prasad, Shirshendu Das, Hemangee K. Kapoor
2013DASCTowards a Better Cache Utilization Using Controlled Cache Partitioning.Prateek D. Halwe, Shirshendu Das, Hemangee K. Kapoor
2010VLSIDExploring Use of NoC for Reconfigurable Video Coding.Alpesh Patel, Hemangee K. Kapoor
2006SEFMFormal Modelling and Verification of an Asynchronous DLX Pipeline.Hemangee K. Kapoor
2004DACDecomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis.Hemangee K. Kapoor, Mark B. Josephs