Heng-Liang Huang
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
3
Active years
2000–2025
Best venue rank
B
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ASPDAC | ResCap: Fast-yet-Accurate Capacitance Extraction for Standard Cell Design by Physics-Guided Machine Learning. | Jiun-Cheng Tsai, Hsuan-Ming Huang, Wei-Min Hsu, Pei-Ting Lee, Jen-Hang Yang, Heng-Liang Huang, Yen-Ju Su, Charles H.-P. Wen |
| 2025 | ICCAD | MuSTNet: SAT-based Exact Multi-Stage Transistor Network Synthesis with Placement Awareness. | Jiun-Cheng Tsai, Wei-Min Hsu, Kuei-Lin Wu, Hsuan-Ming Huang, Jen-Hang Yang, Heng-Liang Huang, Yen-Ju Su, Charles H.-P. Wen |
| 2024 | ICCAD | MAXCell: PPA-Directed Multi-Height Cell Layout Routing Optimization using Anytime MaXSAT with Constraint Learning. | Jiun-Cheng Tsai, Wei-Min Hsu, Yun-Ting Hsieh, Yu-Ju Li, Wei Huang, C. N. Ho, Hsuan-Ming Huang, Jen-Hang Yang, Heng-Liang Huang, Aaron C.-W. Liang, Charles H.-P. Wen |
| 2004 | ISCAS | An efficient logic extraction algorithm using partitioning and circuit encoding. | Lily Huang, Tai-Ying Jiang, Jing-Yang Jou, Heng-Liang Huang |
| 2001 | ISCAS | Grouped input power sensitive transition an input sequence compaction technique for power estimation. | Heng-Liang Huang, Yeong-Ren Chen, Jing-Yang Jou, Wen-Zen Shen |
| 2000 | ASPDAC | A new method for constructing IP level power model based on power sensitivity. | Heng-Liang Huang, Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou |