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MuSTNet: SAT-based Exact Multi-Stage Transistor Network Synthesis with Placement Awareness.

Jiun-Cheng Tsai, Wei-Min Hsu, Kuei-Lin Wu, Hsuan-Ming Huang, Jen-Hang Yang, Heng-Liang Huang, Yen-Ju Su, Charles H.-P. Wen

VenueAICCAD
Year2025
ProceedingsICCAD

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