| 2022 | AAAI | On the Practical Robustness of the Nesterov's Accelerated Quasi-Newton Method. | S. Indrapriyadarsini, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai |
| 2022 | AAAI | A Stochastic Momentum Accelerated Quasi-Newton Method for Neural Networks (Student Abstract). | S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai |
| 2020 | ISCAS | A Neural Network Approach to Analog Circuit Design Optimization using Nesterov's Accelerated Quasi-Newton Method. | S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai |
| 2019 | ICMLA | A Stochastic Variance Reduced Nesterov's Accelerated Quasi-Newton Method. | Sota Yasuda, Shahrzad Mahboubi, S. Indrapriyadarsini, Hiroshi Ninomiya, Hideki Asai |
| 2019 | PRICAI | Momentum Acceleration of Quasi-Newton Training for Neural Networks. | Shahrzad Mahboubi, S. Indrapriyadarsini, Hiroshi Ninomiya, Hideki Asai |
| 2018 | ICMLA | Implementation of a Modified Nesterov's Accelerated Quasi-Newton Method on Tensorflow. | S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Hideki Asai |
| 2014 | ASPDAC | HIE-block latency insertion method for fast transient simulation of nonuniform multiconductor transmission lines. | Takahiro Takasaki, Tadatoshi Sekine, Hideki Asai |
| 2013 | ASPDAC | Unconditionally stable explicit method for the fast 3-D simulation of on-chip power distribution network with through silicon via. | Tadatoshi Sekine, Hideki Asai |
| 2012 | ASPDAC | Predictor-corrector latency insertion method for fast transient analysis of ill-constructed circuits. | Hiroki Kurobe, Tadatoshi Sekine, Hideki Asai |
| 2010 | ASPDAC | A novel FDTD algorithm based on alternating-direction explicit method with PML absorbing boundary condition. | Shuichi Aono, Masaki Unno, Hideki Asai |
| 2010 | DATE | Equivalent circuit modeling of multilayered power/ground planes for fast transient simulation. | Takayuki Watanabe, Hideki Asai |
| 2008 | ASPDAC | Generating stable and sparse reluctance/inductance matrix under insufficient conditions. | Yuichi Tanji, Takayuki Watanabe, Hideki Asai |
| 2007 | ISCAS | Application of Relaxation-Based Technique to ADI-FDTD Method and Its Estimation. | Yuya Nakazono, Hideki Asai |
| 2006 | ASPDAC | Parallel-distributed time-domain circuit simulation of power distribution networks with frequency-dependent parameters. | Takayuki Watanabe, Yuichi Tanji, Hidemasa Kubota, Hideki Asai |
| 2006 | CEC | Two-staged Tabu Search for Floorplan Problem Using O-Tree Representation. | Hiroshi Ninomiya, Kimihiko Numayama, Hideki Asai |
| 2006 | DATE | Large scale RLC circuit analysis using RLCG-MNA formulation. | Yuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai |
| 2006 | ISCAS | Fast timing analysis of plane circuits via two-layer CNN-based modeling. | Yuichi Tanji, Hideki Asai, Masayoshi Oda, Yoshifumi Nishio, Akio Ushida |
| 2005 | CEC | Three dimensional module packing by simulated annealing. | Hirokazu Yamagishi, Hiroshi Ninomiya, Hideki Asai |
| 2005 | IJCNN | An efficient learning algorithm for finding multiple solutions based on fixed-point homotopy method. | Hiroshi Ninomiya, Chikahiro Tomita, Hideki Asai |
| 2005 | ISCAS | Modified hybrid reduction technique for the simulation of linear/nonlinear mixed circuits. | Takashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai |
| 2005 | ISCAS | Modeling of power distribution networks with signal lines for SPICE simulators. | Takayuki Watanabe, Hideki Asai |
| 2004 | DAC | Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects. | Yuichi Tanji, Hideki Asai |
| 2004 | DATE | Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits. | Takashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai |
| 2003 | ASPDAC | Behavioral modeling of EM devices by selective orthogonal matrix least-squares method. | Yuichi Tanji, Masaya Suzuki, Takayuki Watanabe, Hideki Asai |
| 2003 | IJCNN | An efficient learning algorithm with second-order convergence for multilayer neural networks. | Hiroshi Ninomiya, Chikahiro Tomita, Hideki Asai |
| 2003 | ISCAS | Analysis of PCB interconnects using electromagnetic reduction technique. | Takayuki Watanabe, Hideki Asai |
| 2002 | ISCAS | Optimal placement of decoupling capacitors on PCB using Poynting vectors obtained by FDTD method. | I. Hattori, Atsushi Kamo, Takayuki Watanabe, Hideki Asai |
| 2002 | ISCAS | Noise analysis of power/ground planes on PCB by SPICE-like simulator with model order reduction technique. | Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai |
| 2002 | ISCAS | A threshold voltage independent floating resistor circuit exhibiting both positive and negative resistance values. | Takao Oura, Teru Yoneyama, Shashidhar Tantry, Hideki Asai |
| 2001 | ISCAS | High-speed interconnect simulation using MIMO type of adaptive least square method. | Masaya Suzuki, Hirofumi Miyashita, Atsushi Kamo, Takayuki Watanabe, Hideki Asai |
| 2001 | ISCAS | Simulation for the optimal placement of decoupling capacitors on printed circuit board. | Atsushi Kamo, Takayuki Watanabe, Hideki Asai |
| 2001 | ISCAS | Two floating resistor circuits and their applications to synaptic weights in analog neural networks. | Shashidhar Tantry, Teru Yoneyama, Hideki Asai |
| 2000 | IJCNN | Design Method of Limit Cycle Generator by Hysteresis Neural Networks. | Teru Yoneyama, Hideki Asai, Hiroshi Ninomiya |
| 2000 | IJCNN | Neuro-Based Human-Face Recognition with 2-Dimensional Discrete Walsh Transform. | Masahiro Yoshida, Hideki Asai, Takeshi Kamio |
| 1999 | IJCNN | A neuro-based optimization algorithm for tiling problems with rotation. | Shinsuke Manabe, Hideki Asai |
| 1999 | IJCNN | Design method of neural networks for limit cycle generator. | Teru Yoneyama, Hiroshi Ninomiya, Hideki Asai |
| 1999 | ISCAS | Expanded GMC for transient analysis of transmission line networks. | Atsushi Kamo, Takayuki Watanabe, Hideki Asai |
| 1999 | ISCAS | Efficient synthesis technique of time-domain models for interconnects having 3-D structures based on FDTD method. | Takayuki Watanabe, Hideki Asai |
| 1995 | ISCAS | Convergence of Hopfield Neural Network for Orthogonal Transformation. | Takeshi Kamio, Hiroshi Ninomiya, Hideki Asai |
| 1995 | ISCAS | Orthogonalized Steepest Descent Method for Solving Nonlinear Equations. | Hiroshi Ninomiya, Hideki Asai |
| 1994 | ISCAS | Transient Simulation of Coupled Lossy Interconnects by Window Partitioning Technique. | Vijaya Gopal Bandi, Hideki Asai |
| 1994 | ISCAS | Iterated Timing Analysis with Dynamic Partitioning Technique for Bipolar Transistor Circuits. | Masaki Ishida, Koichi Hayashi, Masakatsu Nishigaki, Hideki Asai |
| 1994 | ISCAS | Mixed Mode Circuit Simulator SPLIT2.1 using Dynamic Network Separation and Selective Trace. | Masakatsu Nishigaki, Nobuyuki Tanaka, Hideki Asai |
| 1994 | ISCAS | Relaxation-Based Steady-State Analysis of Single- and Multi-Conductor Transmission Lines in Frequency Domain. | Takeshi Senoo, Hiroaki Makino, Hideki Asai |