| 2025 | DAC | Late Breaking Results: Novel Design of MTJ-Based Unified LIF Spiking Neuron and PUF. | Milad Tanavardi Nasab, Wu Yang, Himanshu Thapliyal |
| 2025 | ISCAS | Crosstalk Attack Resilient RNS Quantum Addition. | Bhaskar Gaur, Himanshu Thapliyal |
| 2025 | ISCAS | Detection of Physiological Data Tampering Attacks with Quantum Machine Learning. | Md. Saif Hassan Onim, Himanshu Thapliyal |
| 2025 | QCE | Residue Number System (RNS) Based Distributed Quantum Multiplication. | Bhaskar Gaur, Himanshu Thapliyal |
| 2023 | QCE | GTQCP: Greedy Topology-Aware Quantum Circuit Partitioning. | Joseph Clark, Travis S. Humble, Himanshu Thapliyal |
| 2020 | ICCD | Special Session: A Novel Low-Power and Energy-Efficient Adiabatic Logic-In-Memory Architecture Using CMOS/MTJ. | Himanshu Thapliyal, S. Dinesh Kumar |
| 2020 | ICCD | Special Session: Quantum Carry Lookahead Adders for NISQ and Quantum Image Processing. | Himanshu Thapliyal, Edgard Muoz-Coreas, Vladislav Khalus |
| 2017 | ISCAS | Design of majority logic based approximate arithmetic circuits. | Carson Labrado, Himanshu Thapliyal, Fabrizio Lombardi |
| 2017 | ISCAS | Energy-efficient magnetic circuits based on nanoelectronic devices. | Fazel Sharifi, Himanshu Thapliyal |
| 2017 | VLSID | Heuristic Based Majority/Minority Logic Synthesis for Emerging Technologies. | Vipul Kumar Mishra, Himanshu Thapliyal |
| 2014 | VLSID | Design of Dedicated Reversible Quantum Circuitry for Square Computation. | H. V. Jayashree, Himanshu Thapliyal, Vinod Kumar Agrawal |
| 2014 | VLSID | Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits. | Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan |
| 2012 | DATE | Mach-Zehnder interferometer based design of all optical reversible binary adder. | Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan |
| 2012 | VLSID | Tutorial T2: Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future. | Himanshu Thapliyal, Nagarajan Ranganathan |
| 2011 | DATE | A new reversible design of BCD adder. | Himanshu Thapliyal, N. Ranganathan |
| 2010 | VLSID | Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs. | Himanshu Thapliyal, Nagarajan Ranganathan |
| 2009 | ISCAS | Concurrently Testable FPGA Design for Molecular QCA using Conservative Reversible Logic Gate. | Himanshu Thapliyal, Nagarajan Ranganathan |
| 2009 | VLSID | Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits. | Himanshu Thapliyal, Nagarajan Ranganathan |
| 2007 | ISCAS | Design of Reversible Sequential Elements With Feasibility of Transistor Implementation. | Himanshu Thapliyal, A. Prasad Vinod |
| 2007 | ISCAS | Designing Efficient Online Testable Reversible Adders With New Reversible Gate. | Himanshu Thapliyal, A. Prasad Vinod |
| 2007 | PDPTA | Combined Integer and Variable Precision (CIVP) Floating Point Multiplication Architecture for FPGAs. | Himanshu Thapliyal, Hamid R. Arabnia, Rajnish Bajpai, Kamal K. Sharma |
| 2006 | AICCSA | Low Power Hierarchical Multiplier and Carry Look-Ahead Architecture. | Himanshu Thapliyal, Neela Gopi, K. K. Pavan Kumar, M. B. Srinivas |
| 2006 | AICCSA | Novel Reversible Multiplier Architecture Using Reversible TSG Gate. | Himanshu Thapliyal, M. B. Srinivas |
| 2006 | CIT | Design of Novel Reversible Carry Look-Ahead BCD Subtractor. | Himanshu Thapliyal, Sumedha K. Gupta |
| 2006 | VLSID | Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format. | Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas |