| 2024 | ISCAS | A 10-bit 100kS/s SAR ADC With a Monotonic Capacitor Switching Procedure for Single-Ended Inputs in 22nm CMOS FDSOI. | Alexander Meyer, Kaoru Yamashita, Adilet Dossanov, Martin Maier, Finn Stapelfeldt, Yerzhan Kudabay, Peter Toth, Fa Foster Dai, Hiroki Ishikuro, Vadim Issakov |
| 2021 | ASPDAC | Gate Voltage Optimization in Capacitive DC-DC Converters for Thermoelectric Energy Harvesting. | Yi Tan, Yohsuke Shiiki, Hiroki Ishikuro |
| 2021 | ASPDAC | An up to 35 dBc/Hz Phase Noise Improving Design Methodology for Differential-Ring-Oscillators Applied in Ultra-Low Power Systems. | Peter Toth, Hiroki Ishikuro |
| 2021 | ASPDAC | An 18 Bit Time-to-Digital Converter Design with Large Dynamic Range and Automated Multi-Cycle Concept. | Peter Toth, Hiroki Ishikuro |
| 2020 | ISCAS | A High-Resolution Oscillator Based Resistance-to-Digital Converter with Non-Linearity Canceling Feedback by ΔΣ Modulated Variable Resistor. | Shuya Nakagawa, Takumi Miyazaki, Hiroki Ishikuro |
| 2020 | ISCAS | A 0.12V Fully Integrated Charge Pump with Gate Voltage Optimization for Energy Harvesting Applications. | Yi Tan, Yohsuke Shiiki, Hiroki Ishikuro |
| 2020 | ISCAS | A Wide Range and High Accuracy Sensor Interface with Switching Regulator for Coin-Cell Powered Tiny Wireless Sensor Node. | Kohei Tatehora, Yohsuke Shiiki, S. Nakagawa, Takahisa Tanaka, Ken Uchida, Hiroki Ishikuro |
| 2019 | ISCAS | Interface with Opamp Output-Impedance Calibration Technique for a Large Integrated 2-D Resistive Sensor Array. | Yohsuke Shiiki, Hiroki Ishikuro |
| 2018 | ASPDAC | Design of resource sharing reconfigurable ΔΣ SAR-ADC. | Motomi Ishizuka, Kohei Yamada, Hiroki Ishikuro |
| 2016 | ISCAS | Low power DT delta-sigma modulator with ring amplifier SC-integrator. | Takuma Suguro, Hiroki Ishikuro |
| 2015 | ASPDAC | Dual-output wireless power delivery system for small size large volume wireless memory card. | Junki Hashiba, Toru Kawajiri, Yuya Hasegawa, Hiroki Ishikuro |
| 2014 | ASPDAC | An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique. | Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro |
| 2013 | ASPDAC | A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched Transmission Line Couplers and Dicode partial-response channel transceivers. | Atsutake Kosuge, Wataru Mizuhara, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda |
| 2013 | ASPDAC | A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC. | Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro |
| 2013 | ISCAS | A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL. | Yuki Urano, Won-Joo Yun, Tadahiro Kuroda, Hiroki Ishikuro |
| 2013 | ISCAS | A voltage scaling 0.25-1.8 V delta-sigma modulator with inverter-opamp self-configuring amplifier. | Kentaro Yoshioka, Yosuke Toyama, Teruo Jyo, Hiroki Ishikuro |
| 2009 | ASPDAC | A wireless real-time on-chip bus trace system. | Shusuke Kawai, Takayuki Ikari, Yutaka Takikawa, Hiroki Ishikuro, Tadahiro Kuroda |