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A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC.

Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro

VenueBASPDAC
Year2013
ProceedingsASP-DAC

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