A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC.
Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro
Browse the full ASPDAC paper archive.
Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro
Browse the full ASPDAC paper archive.